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This paper presents a theoretical and experimental analysis of the capabilities of the dual-input Doherty power amplifier (DPA) architecture to mitigate efficiency and output power degradations when used in a mismatched load environment. Following a simplified linear piecewise approach, an analytical demonstration is proposed to derive optimal radio frequency drives applied to the Auxiliary path of the DPA to restore power performances while avoiding large signal voltage clipping of active cells. The proposed analytical study is corroborated with harmonic balance simulated results of a C-band, 20-W GaN DPA prototype. The fabricated dual-input DPA prototype has been measured under 1.5-VSWR mismatch configurations to validate the proposed analysis.

International audience; This paper reports on the design of a new power cell dedicated to Ku-band power amplifier (PA) applications. This cell called "integrated cascode" has been designed in order to propose a strong decrease in terms of circuit size for PA. The technology used relies on 0.25-μm GaAs pseudomorphic high electron mobility transistors (PHEMT) of United Monolithic Semiconductors (UMS) foundry. A distributed approach is proposed in order to model this power cell. The challenge consists of obtaining, with a better shape factor (ratio between the vertical and horizontal sizes of the transistor), the same performances than a single transistor with the same gate width. In order to design a 2W amplifier, we have used two 12 × 100 μm transistors. Cascode vertical size is 413 μm whereas a transistor with the same gate width exhibits a vertical size of 790 μm. Therefore, the shape factor is nearly one as compared to a shape factor of 4 for a classical parallel architecture. This new device allows us to decrease the Monolithic microwave integrated circuit amplifier area of 40% compared to amplifier based on single transistors.

International audience; The design of high speed integrated circuits heavily relies on circuit simulation and requires compact transistor models. This paper presents a non-linear electro-thermal model of SiGe heterojunction-bipolar transistor (HBT). The non-linear model presented in this paper uses a hybrid π topology and it is extracted using IV and S-parameter measurements. The thermal sub-circuit is extracted using low-frequency S-parameter measurements. The model extraction procedure is described in detail. It is applied here to the modeling of npn SiGe HBTs. The proposed non-linear electro-thermal model is expected to be used for the design of high-speed electronic functions such as broadband analog digital converters in which both electrical and thermal aspects are engaged. The main focus and contribution of this paper stands in the fact that the proposed non-linear model covers wideband-frequency range (up to 65 GHz).

International audience; The electrical modeling of power packages is a major issue for designers of high-efficiency hybrid power amplifiers. This paper reports the synthesis and the modeling of a packaged Gallium nitride (GaN) High electron mobility transistor (HEMT) associating a nonlinear model of the GaN HEMT die with an equivalent circuit model of the package. The extraction procedure is based on multi-bias S-parameter measurements of both packaged and unpackaged (on-wafer) configurations. Two different designs of 20 W packaged GaN HEMTs illustrate the modeling approach that is validated by time-domain load-pull measurements in S-band. The advantage of the electrical modeling dedicated to packaged GaN HEMTs is to enable a die-package co-design for power matching. Internal matching elements such as Metal oxide semiconductor (MOS) capacitors, Monolithic microwave integrated circuits (MMICs), and bond wires can be separately modeled to ensure an efficient optimization of the package for high power Radio frequency (RF) applications.

The present paper presents the transistor modeling work achieved in the GaN European project KorriGaN (“Key Organisation for Research in Integrated Circuits in GaN technology”). The KorriGaN project (2005–09) has released 29 GaN circuits such as high-power amplifiers (HPAs), low-noise amplifiers (LNAs), and switches. Modeling is one of the main key to reach successful designs. Therefore, nonlinear models of European GaN HEMT models have been developed. This work deals with characterization tools such as pulsed IV, pulsed [S] parameters, load-pull measurements, and measurement-based methods to perform GaN HEMT compact models parameters extraction. The present paper will describe the transistor modeling activities in KorriGaN for HPA designs (nonlinear models including trapping and/or self-heating effects) and LNA designs (nonlinear models and noise parameters).