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In this paper, the effect of a metal patterned ground shield (PGS) on the performance of monolithic inductors is investigated. To this aim, three spiral inductors integrated in a 28‐nm fully depleted (FD) silicon‐on‐insulator (SOI) CMOS technology are analyzed by means of a 3‐D FEM‐based commercial software. The inductors have been designed at different operating frequencies in the RF and mm‐wave ranges to better explore the effect of the PGS. Extensive analysis revealed that the shield is able to improve the quality factor (Q‐factor) only of the inductor operated at the lowest frequency (ie, K‐band). On the contrary, it has a detrimental effect on the Q‐factor of the inductors working at higher frequencies. This is mainly due to induced losses in the PGS itself, which are so high to frustrate the substrate loss reduction. This result gives a different perspective to the adoption of the PGS for CMOS integrated inductors, which is largely recommended to improve inductor performance in the current state of the art. [ABSTRACT FROM AUTHOR]

A lumped scalable model of silicon integrated inductors for RF IC design is presented. It was validated up to 20 GHz using measured performance parameters of more than 70 single-ended and differentially driven spirals covering 0.2- to 8.3 nH inductance values. Excellent accuracy, full geometrical scalability, compactness and high capability for implementation in circuit simulators promote the proposed model as a reliable time-saving design tool. Two circuital example, i.e., 5-GHz down-converter and 10-GHz VCO, are also presented to demonstrate its use in practical cases. © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009. [ABSTRACT FROM AUTHOR]