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System in Package (SiP) modules provide integrated functionalities (processor, memory, power, etc.) in a small form factor as compared to PCB based individually laid out packages and passives. SiP modules face assembly related challenges as the complexity of packages increases (multi die, large number of passives, through mold via interposer for external memory, convergence of different technologies). This paper describes assembly challenges associated with a multi-die flip chip (processor, memory and power) module with plastic interposer for external Package-on-Package (PoP) memory. The prototype test package with three flip chip die was processed using different bump structures with bump height variation and differences in coplanarity. The underfill dispense pattern was optimized to eliminate underfill creep to the top of passive components that could lead to interfacial delamination. The interposer solder had no reliability risk due to the added mechanical strength of the underfill. Laser ablation formed through mold vias (TMV) on top of the interposers to connect to a package on package memory device. Partially defined TMV opening profile, adjacent solder bridging, formation of cold joint due to poor coplanarity, and foreign material contamination concerns were mitigated by tightening design and process parameters for flip chip attach (bump shorting and cold joint), underfill (interposer tilt, voids, material creep, dispense pattern, volume), interposer (tilt, warpage, solder voids), TMV laser ablation process (exposed Cu, depth, width), and mounting of passives components (topography, misalignment, cap solder volume).

A miniaturized antenna is required for a small form factor RFID tag. For harmonic RFID tag, the tag should be capable of receiving and transmitting at two different frequencies (fundamental and harmonic). Implementation of two different antennas for the operation would increase the footprint of the antenna. Hence, an optimized antenna structure is proposed, which will have a small form factor while maintaining a considerable gain. The dual band antenna would be capable of receiving at fundamental frequency and transmit information at harmonic frequency while maintaining small tag size. The dual band antenna has a miniaturized rectangular board dimension of 96.5 mm and 81 mm with resonance at 434 MHz at low frequency and 860 MHz to 1000 MHz at high frequency. The harmonic tag was designed with nonlinear transmission line and the dual band antenna. The harmonic RF tag would be useful for numerous RF applications where the single frequency tags will not be a good option such as underground object tagging, tag detection in an industrial set up with strong reflectors such a metal in the vicinity. In this paper, the design, fabrication and characterization of dual band harmonic RFID tag antenna is presented.

This paper details an architecture that includes a recess in motherboard (RiMB) to enable increased packaging density of functional components for next generation mobile personal computing products. The recess depth, manufacturing methods, and SMT assembly data are included to provide the reader with a full overview of the manufacturing and assembly challenges.

As electronic products become smaller and thinner with increasing number of functions, the demand for high density and high integration becomes stronger. Glass has many properties that make it an ideal substrate for high integration substrate such as; ultra high resistivity, adjustable thermal expansion (CTE) high modulus, low dielectric constant, low dielectric loss and manufacturability with large panel sizes. Multi-bands with carrier aggregation, Wi-Fi/GPS coexistence, and LTE-U make RF front end more and more complicated. 3D IPD (integrated passive devices) on Glass substrate technology could be advantage solution include reducing power consumption and small form factor. This paper presents a demonstration of 3D RF front end filters using 3D solenoid inductors with through glass vias (TGV) and Cu-SiN-Cu MIM structure on Gen1 glass substrate (300mm × 400mm) panel format using color filter manufacturing line for flat panel display. For inductors, drastic performance (size and low resistance therefore high-quality factor) improvement have been demonstrated by technology evolutions from 3D solenoid using TGV with conformal Cu plating method, achieving low resistance of 3.1mohm per 70um diameter TGV on a 400um thick glass panel. This low-resistance TGV with 2.7mOhm/sq TGV connections on both sides of the glass substrate, record high inductor quality factor of 39 was obtained at 2.5GHz using five and half turn inductor of 7.9nH inductance, For capacitors, we have successfully integrated a Cu MIM (metal-insulator-metal) structure by using 15um thick Cu plates and dielectric, resulting in high capacitance density of 0.26nF/mm2 for RF application. By integrating TGV inductor-first and MIM capacitor-next, high-performance and high-density LC components are synthesized to perform as RF front end filters such as low-pass filters, diplexers, triplexers, and multiplexers. The 3D inductors, Cu MIM, LC resonators and filters were successfully integrated using glass panel manufacturing infrastructure for the first time. Process characterization and process control monitors were evaluated at the panel level to address high-volume and high-yield manufacturability of RF filters with the unprecedented filter performance in terms of insertion loss and out of band rejections in smaller form factor than any other technologies have achieved so far. Furthermore, the TGV filters were mounted on electrical evaluation boards as well as JEDEC standard testing boards to check any device-level, chip-level, and board-level reliabilities associated with glass or TGV materials as well as their interaction with Cu, SiN, polymer inter layer dielectric materials, and solder joints, showing no performance degradations during thermal cycling, drop shock, bending, or high-power testing situations.

Cell sorting is an important diagnostic tool used in various aspect of medical prognosis. Numerous cell sorting techniques are currently available on market but they are quite bulky, expensive and at the same time requires very trained operators. In this paper we report on wafer level fabrication technique that will allows for a small form factor device targeting cell sorting. We give detailed overview for the fabrication of our miniaturized cell sorter that is formed with a CMOS compatible process. It used standard fabrication technique in combination with photo-patternable polymer, that has excellent properties for microfluidics applications. The ability to process on wafer level distinguish this from other processes, whose yields are limited to few test samples. The device fabrication includes: processing of micro-heaters, definition of polymer microfluidic channels and collective die-to-wafer bonding of glass substrate onto the polymer channels. We report on the initial characterization of the cell sorting targeting sorting rate and sorting yield. We have achieved sorting rate of 5,000 cells/s and yield of 70% is obtained in initial investigations.

The rapid development in the Internet of Things (IoT) has seen a surge in demand for System-in-Package (SiP), which is capable of packing more functionality into a single package with a small form factor. This continues to push miniaturization to an even greater level, therefore creating assemblies with smaller components and greater density. 01005 passive components are being used in most of the current SiP technology and the industry is looking at utilizing 008004 passive components for the next generation SiP. The stencil aperture design for 008004 will likely be about half of 01005, and a finer powder size solder paste will be used. The stencil design, stencil thickness, and the types of stencils being used, are crucial in achieving good solder paste printing performance. Due to the need of squeezing more components into a SiP, the gap between neighboring pads can be as close as 50μm; hence, it is crucial to avoid solder bridging for such applications. This paper will discuss the challenges in achieving consistent solder paste printing performance for fine feature applications using Type 6 (5–15μm) powder size solder paste. Test results with different stencil designs, printing parameters, and different solder pastes will be discussed in detail.

Voiding under bottom terminated components (BTCs), such as quad-flat no-lead (QFN) components, is a problem which many circuit board assembly houses face on a daily basis. Such components have become very popular in circuit board assembly due to many of their benefits, including their small form factor, excellent thermal and electrical performance, easy PCB trace routing, and reduced lead inductance. Outgassing of flux in the solder paste used to attach QFNs to the PCB during reflow causes voiding under the components, as the gasses cannot escape because there is virtually no standoff under the QFNs. Voiding can have several serious effects on the performance of QFNs including reduced mechanical strength of the solder joint and hot spots under the QFN thermal pad because the voids do not conduct heat well. There are many process methods which are utilized in an attempt to mitigate the voiding issue, such as windowpane stencil designs and reflow profile. In this study, we will evaluate the effect of several other variables on voiding under QFNs, including solder paste powder mesh size, PCB surface metallization, and the reflow environment.

The goal of the development effort was to prove a new way of creating electrical interconnects that enable much higher density, tuned circuits and connectors driven by the demands of future mobile and computing applications, including wearable and connected devices. The primary results obtained are a method to fabricate package substrates, small form factor rigid and flexible circuits using a material used in the connector industry Liquid Crystal Polymer, and linking circuits and connectors with tuned high density performance not possible with legacy manufacturing. Applications will be detailed in conjunction with the Semiconductor companies that demonstrate substrates and circuits that have high aspect ratio traces with 20–50 micron traces surrounded with fusion bonded LCP that enables impedance matching of 1–2% on high density. The study extends further to connector technology that enables interconnect of the subject substrate or circuit directly into mobile and wearable applications with over 1000 high speed interconnects capable of 28–56 Gb/s performance within a 1/2 inch square area. In addition the study will leverage the formable nature of circuit bearing Liquid Crystal Polymer to create interconnected assemblies with integral antennae, decoupling, RF shielding and die to die interconnect ideal for wearable applications.

A new wafer-level 3D system integration process that relies on a novel multi-level 3D redistribution layer technology (3D-RDL) to interconnect chips together as well as to the substrate was developed. The 3D-RDL technology is based on a single electroplating step that allows routing high density, auto-adaptive vertical copper interconnects (20 μm Line/Space “L/S”) at the edge of known-good dies as well as redistribution layer on top of the die and the substrate. Furthermore, this technology enables 3D interconnection of stacked dies using a single 3D-RDL layer. Additionally, high performance 3D inductive devices with small form factor can be integrated above-IC or above-substrate using the same 3D-RDL processing steps. These capabilities allow miniaturization and performance enhancement and make the technology ideal for various applications requiring functional heterogeneous system integration on a small footprint, such as systems for mobile and Internet-of-Things (IoT) applications, MEMS and Sensors.

The use of bottom terminated components (BTCs) such as quad-flat no-leads (QFNs) has become commonplace in the circuit board assembly world. This package offers several benefits including its small form factor, its excellent thermal and electrical performance, easy PCB trace routing, and reduced lead inductance. These components are generally attached to PWBs PCBs via solder paste. The design of these components with the large thermal pad, along with the tendency of solder paste to outgas during reflow from the volatiles in the flux, creates a difficult challenge in terms of voiding control within the solder joint. Voiding can have a serious effect on the performance of these components, including the mechanical properties of the joint as well as spot overheating. Solder preforms with a flux coating can be added to the solder paste to help reduce voiding. This study will focus on the benefits of utilizing solder preforms with modern flux coatings in conjunction with solder paste to help reduce voiding under QFNs, as well as the design and process parameters which provide optimal results.

With the advent of modern and autonomous electronics, applications using RF (radio frequencies) up to millimeter waves and beyond are proliferating. The systems integration becomes increasingly challenging due to variety of devices and passives that typically compose such RF modules, and careful choices of materials are needed for low loss interconnects. One way to minimize RF losses is to integrate the module with high performance interconnect using Si technology, where the different device are mounted on the interposer and the passive are integrated into the silicon. Thanks to the TSV (Through Silicon Via) technology and use of High Resistivity Si substrate, it is possible to have small form factor modules. Such integration approach allows to benefit from the well-established base of 200mm foundries together with the recent progress made in High Resistivity substrate manufacturing. In this work, the process development of a 3D RF interposer technology based on a 200mm process line is reported. The build-up contains 2 levels of metals processed by Cu damascene technology, including a thick 2μm top metal for the lower frequencies applications, an integrated MIM (Metal Insulator Metal) capacitor and use trough silicon via in 5kOhm high resistivity 85μm thick substrate. The TSV are 20μm diameter and 85μm deep made in via first manner with via reveal using temporary carrier handling. Various RF passivation techniques for the silicon have been investigated and a comparison to quartz based on similar test structure is discussed.. Variety of passive devices, transmission line and filter have been processed and characterized. The technology yields 1μm pitch interconnect routing layer, a line loss of 0.34 dB/mm at 40 GHz, and high quality factors inductors larger than 30.

For many military applications, domestic sourcing for passive electronic components are required. Organizations wrestling with the loss of domestic electronic parts producers, have a solution in nano fabricated components. This highly reliable technology employs the use of COTS raw materials sets, mitigating development risk. Application flexible, existing surface mounted components can be replaced with this superior technology. The unique construction of this nano fabricated product enables board space reductions exceeding 65%, a critical advantage in space applications.

Based on Wire-free Die on Die disruptive technology (WDoD™), high density memory can be manufactured in a small form factor package size. Stacking known good rebuilt wafers allows high yields while integrating high performance devices. Dual die (DD) and Quad die (QD) DDR3 memories exhibit outstanding performance and show the path to highly densified System in Package (SiP) for Medical, Defense and Industrial markets

This paper presents the process challenges for the fabrication of 0-level packages using chip capping with through silicon via's (TSV) in the capping chip/wafer. The key processing challenges addressed include the fabrication of TSVs on capping wafers that are thinned down to 100μm and further, the Cu/Sn/Cu diffusion soldering to make an intermetallic bond for the chip capping. Integration of the TSVs on the cap wafer enables the vertical interconnection, thus making the package with a small form factor and readiness for 3D integration. The Cu/Sn/Cu bond and seal process provides a hermetic package and at the same time provide electrical connection between the cap and the device wafer. Adequate processing conditions are proposed.

In this paper, the novel use of Parylene for implantable biomedical microsystems packaging is presented. Parylene is an excellent candidate material to be used for implantable and clinically usable miniature devices due to its biocompatibility, flexibility, near-hermeticity, and high-density integration capability in a small form factor. Here, we propose a novel all-Parylene packaging technique where Parylene is used as a package substrate, an isolation layer, a capacitor insulator, and a sealing layer. Fully-integrated embedded passive devices, transmission lines, and surface mount components on a thin-film multilayer Parylene substrate are described. Metal-insulator-metal capacitors are implemented on Parylene and their DC and RF properties are characterized. Further, high-density 3-D trench capacitors are developed on Parylene for the first time. By integrating embedded capacitors and antenna with surface mount diodes, a rectifier module is implemented. Wireless powering onto the Parylene package is demonstrated as a proof-of-concept for the implant package to be powered by external environment. The authors believe that the all-Parylene packaging method described here can be widely applied to other miniature implant applications.

In this paper, we present some passive components made from silicon substrate technology (Integrated Passive Device process) and integration schemes using these components for RF applications. RF decoupling capacitors from this process are characterized on ESR and ESL performance. Functional blocks (filters, baluns, diplexers, matching, etc) made from the IPD process, have shown good electrical performance with small form-factor features. The thin profiles from the IPDs make them very suitable to be used inside laminate and QFN packages. System-in-Packages or multiple-chip-modules using IPD approaches may have significant size reduction. The low profiles and the small form-factors of the IPDs result in less cross-talk between the IPDs and their nearby components (chips, SMDs, and routing traces, etc), and therefore it is easier to maintain signal integrity for packages.

Flip chip thermosonic back end assembly method is a low cost clean gold to gold interconnection method. The advancement of flip chip thermosonic process for CSP packaging of HBLED and CMOS image sensors is occurring due to the precision intermetallic clean interconnection properties and ability to provide a small form factor packaging to consumer products. This paper will investigate thermosonic metal to metal interconnection process for these high growth assembly markets. Thermosonic bonding uses a micro weld interconnection die attach method at lower bonding temperature (150°C). The thermosonic metal to metal interconnection method is lead free and the process does not use flux or solder alloys. Thermosonic flip chip die attach process uses a robust individual die “scrubbing” process which reduces assembly steps and eliminates the mass reflow oven used commonly in C4 solder process. The metal to metal interconnection method provides excellent thermal performance for HBLEDs which require the Tj peak temperature to be controlled to maximize device MTBF and overall color temperature performance. The uses of metal to metal interconnection method provide superior thermal performance when compared to solder alloys. The metal to metal interconnection method provides high precision with low particle generation for high performance bonding of CMOS image die using a low-k dielectric wafer. The line spacing for the substrate is 50 μm / 50 μm. Stud bumping machines have a ball placement accuracy of +/− 2.5 μm. Thermosonic GGI die bonders have a mounting accuracy of +/−7 μm. Thermosonic bonding has fast process bonding times of < 500 msec which is important productivity factor in cost sensitive cell phone camera and flash modules.

Cu pillar is an emerging interconnect technology which offers many advantages compared to traditional packaging technologies. This paper presents a novel packaging solution with periphery fine pitch Cu pillar bumps for low cost and high performance Field Programmable Gate Array (FPGA) devices. Wire bonding has traditionally been the choice for low cost implementation of memory interfaces and high speed transceivers. Migration to Cu pillar technology is mainly driven by increasing demand for IO density and package small form factor. Cu pillar bumps also offer significant improvement on electrical performance compared to wire bonds. This paper presents Cu pillar implementation in an 11×11mm flip chip CSP package. Package design is optimized for serial data transport up to 6.114Gbps to meet CPRI_LVII and PCIe Gen2 compliance requirements. Package design strategy includes die and package co-design, SI/PI modeling and physical layout optimization.