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Summary: Synchrophasor technology has received considerable attention in the past few years due to its unique ability to characterize the dynamics of power systems and therefore this paper proposes a low computational cost method to estimate harmonic synchronized phasors for electrical power systems monitoring. The main goal is to estimate the synchronized magnitude, phase, and frequency not only for the fundamental frequency but also for the harmonic components of the signals. Such method is simple to deploy in embedded platforms with limited computation resources and hence it is suitable for the development of low‐cost phasor measurement units (PMUs), which are particularly relevant for applications in distribution systems. The proposed approach makes use of the Fast Fourier Transform along with a hardware‐based scheme in order to mitigate the spectrum leakage effect. This approach consists in a dynamic sampling rate based on the estimated fundamental frequency of the power system. Several experiments were carried out with the proposed method implemented in a general‐purpose hardware development platform, and include the analysis of synchronized harmonic phasor estimation, tests based on the IEEE C37.118.1 PMU standard and the recordings of real power system events. Results show significant error reductions with low computational cost, making it possible to monitor synchronized harmonics, fulfill the requirements of a class P PMU and record power systems events with similar performance to commercial PMU devices. [ABSTRACT FROM AUTHOR]

Summary: Most of the proposed algorithms for synchrophasor estimation are based on the Discrete Fourier Transform (DFT). However, this technique has well‐known limitations, such as the leakage effect. Alternatively, this paper presents a positive‐sequence synchrophasor measurement algorithm based on a Synchronous Reference Frame Phase‐Locked Loop (SRF‐PLL). The algorithm is modular and consists of four stages. The first one is the abc‐dq transform that, with the aid of the second stage, a Finite Impulse Response (FIR) provides the positive‐sequence of the grid voltages. The filter also helps to improve the signal‐to‐noise ratio. This filter class was chosen due to its characteristic of linear phase and constant group delay to avoid unwanted phase distortions at the measurements. The third stage is an SRF‐PLL based on a PID controller that estimates the amplitude and phase of the grid voltage's positive‐sequence component and the grid frequency. By assessing the dynamic condition tests, it was observed that the PLL could not comply with all the IEEE standard requirements. Therefore, a fourth stage was included to calculate the frequency, and Rate of Change of Frequency (ROCOF) based on the estimated positive‐sequence phase. Experimental results obtained with a test platform shown that the proposed algorithm complies with all IEEE C37.118.1‐2011 and C37.118.1a‐2014 standard requirements. [ABSTRACT FROM AUTHOR]