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In this paper, the impact of hot carrier stress on the mismatch properties of n and p metal–oxide–semiconductor (MOS) field-effect transistors (FETs) with different sizes produced using 0.15 µm complementary MOS (CMOS) technology is presented for the first time. The research reveals that hot-carrier injection (HCI) does degrade the matching properties of MOSFETs. The degree of degradation closely depends on the strength of the HC effect. Thus, it is found that, under the stress condition of drain avalanche hot carrier (DAHC), the properties of nMOSFETs rapidly and greatly become worse, but the changes are small for pMOSFETs. For analog circuit parameters, it is found that the after-stress lines of n and pMOSFETs exhibit a cross point in σ (ΔVt,op) drawings. It is suggested that the cross point can be used to indicate the minimal size in order for n and p pairs to have the same degree of ΔVt,op mismatch in designing analog circuits. In addition, interpretations for the differences between n and pMOSFETs and between ΔVt,op and Ids,op mismatches are provided with experimental verifications.

With an increase of power dissipation and integrated-circuit (IC) density in system-on-a-Chip (SoC), it is not sufficient to determine complementary metal-oxide-semiconductor (CMOS) device lifetime by merely monitoring stress-bias conditions, such as hot-carrier (HC) stress. The temperature effect is a significant factor affecting the device lifetime. More and more evidence has been reported which indicates the significance of the temperature effect on device reliability, particularly the negative bias and temperature instability (NBTI) in p-channel metal-oxide-semiconductor field-effect transistors (pMOSFETs). In this work, a complete test of seven kinds of stress conditions which affect device lifetime will be carried out for 0.18 µm generation SoC technology CMOS devices with multiple oxide thicknesses and multiple applied biases. Based on these results, we provide guidelines for next-generation SoC CMOS technology. In nMOSFETs, the temperature effect is weak and therefore conventional hot carrier (HC) stress (i.e., maximum substrate current stress, IB,max) at room temperature dominates the device lifetime. However, in pMOSFETs, the temperature effect is critically important for determining the device lifetime. It was found that NBTI-like HC stress (VG=VD at high-T) has been shown to dominate the device lifetime for both 0.18 µm and 0.35 µm pMOSFETs. Furthermore, the NBTI effect will become more pronounced with the device channel length scaling.

In this study, n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) having 20 and 32 A gate oxide thicknesses of 0.13 µm technology were used to investigate DC hot-carrier reliability at elevated temperatures up to 125 °C. The research also focused on the degradation of analog properties after hot-carrier injection. On the basis of the results of experiments, the hot-carrier degradation of Id,op (drain current defined on the basis of analog applications) is found to be the worst case among those of three types of drain current from room temperature to 125 °C. This result should provide valuable insight to analog circuit designers. As to the reverse temperature effect, the substrate current (Ib) commonly accepted as the parameter for monitoring the drain-avalanche-hot-carrier (DAHC) effect should be modified since the drain current (Id) degradation and Ib variations versus temperature have different trends. For the devices having a gate oxide thinner than 20 A, we suggest that the worst condition in considering hot-carrier reliability should be placed at elevated temperatures.

The effect of post-thermal annealing (PA) after In-halo and As-halo implantation on the reliability of sub-0.1 µm complementary metal-oxide-semiconductor field-effect-transistors was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving hot-carrier-induced device's degradation. The optimal results of device performance as well as of reliability can be obtained with post-annealing treatment performed at medium temperatures (e.g., 900°C) for a longer time.