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In this paper, we briefly review the use of carbon nanotubes and semiconductor nanowires, which represent a new class of nanomaterials actively studied for thin film transistors and electronics applications. Although these nanomaterials are usually synthesised at moderate to high temperatures, they can be transferred to any kind of substrate after growth, paving the way for the fabrication of flexible displays and large area electronics systems on plastic. Over the past few years, the field has progressed well beyond the realisation of elementary devices, since active matrix displays driven by nanowire thin film transistors have been demonstrated, as well as the fabrication of medium scale integrated circuits based on random arrays of carbon nanotubes. Also, graphene, a new nanomaterial has appeared in the landscape; although it is a zero gap semiconductor, it can still be used to make transistors, provided narrow ribbons or bilayers are used. Graphene is also a serious contender for the replacement of oxide-based transparent conducting films.

Interface state creation, induced by hot hole injection, has been frequently observed in n-channel polysilicon thin-film transistors, when subjected to prolonged bias stress with negative gate biases. In this work we propose a new model for the kinetics of interface state formation, that closely links the interface state generation to the measured gate leakage current. The interface state generation mechanism appears to be driven by the recombination of hot holes (injected from the semiconductor active layer) with electrons (injected from the gate electrode). This model is shown to fit very well the time evolution of the interface states, as determined by the sheet conductance of the damaged region close to the drain.

The kinetics of crystallization of high-purity amorphous and mixed-phase silicon films obtained by pyrolysis of disilane gas in the millitorr pressure range were studied. A combination of in situ electrical conductance measurements and transmission electron microscopy analysis was used to determine the crystallization parameters. For mixed-phase films we report an activation energy for the nucleation rate of the order of 2.9 eV, compared to approximately 3.7 eV for the completely amorphous ones; the activation energy for the growth rate is roughly equal to 2.7 eV for the two types of films analyzed.

The deposition of high electrical quality SiO2 films on Si wafers has been achieved without substrate heating, (T2/SiH4) on the dielectric behavior of DECR SiO2. The electrical performances of both Si-SiO2 interfaces and SiO2 films in metal-oxide-semiconductor (MOS) structures were assessed by several characterization methods including critical field (E c) evaluation, fixed charge densities (Q ox) and interface traps densities (D it) determinations. We report typical values of E c around 6 MV·cm-1, and Q ox and D it densities around 2×1010 cm-2 and 3×1010 cm-2·eV-1 respectively. Thin film SOI-MOSFETs have also been fabricated to prove the DECR oxide quality.