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We have investigated the stability of short-channel (1.5 µm) p-type polycrystalline silicon (poly-Si) thin film transistors (TFTs) under AC bias stress. The threshold voltage of the short-channel (L=1.5 µm) poly-Si TFT was increased by about -7.44 V after AC bias stress, whereas the threshold voltage of the long-channel poly-Si TFT was relatively stable. A two-step degradation process was also observed. In the first step, the threshold voltage of short-channel poly-Si TFTs underwent a consistent positive shift for 100 s. In contrast, the threshold voltage started to undergo a negative shift when accompanied by significant degradation in the subthreshold region. This negative shift of threshold voltage and the significantly degraded subthreshold swing value in the short-channel TFT under dynamic stress may be mainly due to the generation of stress-induced deep- and shallow-level trapping states near the drain junction.

We have investigated the reliability of short-channel (L = 1.5 µm) p-type excimer-laser-annealed (ELA) polycrystalline silicon (poly-Si) TFTs under hot-carrier related static bias stress. The threshold voltage (ΔV TH = 0.59 V) of short-channel TFTs (L = 1.5 µm) was significantly more shifted to the positive direction than that (ΔV TH = 0.02 V) of long-channel TFTs (L = 7 µm) under the same stress condition for 100 s. This positive shift of threshold voltage may be attributed to electron trapping at the interface between the poly-Si film and the gate oxide layer. In addition, we have extracted the length of the drain extension from an equation of the pseudo-lightly doped drain (LDD) model to verify the existence of free hole charges induced near the drain junction. The transfer characteristics of the normal and drain-source swapped modes as well as the capacitance–voltage (C–V) characteristics with variation in channel length after the bias stress indicate that the electron trapping at the gate insulator/channel interface mainly occurred near the drain junction region. Furthermore, the threshold voltage of the short-channel ELA poly-Si TFTs with L = 1.5 µm was largely increased as the stress temperature was increased from room temperature to 100 °C, which indicates that the impact ionization occurs more at higher temperature.

We investigated the electrical al characteristics of laser-crystallized polycrystalline silicon thin-film transistors (poly-Si TFTs) under various stresses, such as bias, temperature, and light illumination. The threshold voltage of the short-channel TFTs (L CH = 1.5 µm) was significantly shifted in the negative direction owing to bias temperature stress (ΔV TH = -3.75 V) compared with that found in long-channel TFTs (ΔV TH = -0.32 V) at 100 °C. We also investigated the effects of light illumination on laser-crystallized poly-Si TFTs. In order to improve the reliability of laser-crystallized poly-Si TFTs, we developed a multiple-channel structure fabricated without using any additional processes.

A new bidirectional T-shaped triple-gate device structure, which suppresses the kink effect of sequential lateral solidification (SLS)-processed polycrystalline silicon thin film transistors (poly-Si TFTs), is proposed and fabricated without any additional process. The proposed poly-Si TFTs have a lateral grain growth in channels, similar to TFTs fabricated by SLS or continuous wave (CW) laser crystallization. The whole current flow of the proposed device is mainly affected by the grain boundaries of lateral grain growth. The bidirectional T-shaped triple-gate structure has incorporated a channel located parallel to the lateral grain growth direction, and the another channel located vertically to the lateral grain growth direction. It is verified from experimental and simulation results that the proposed bidirectional T-shaped triple-gate TFT effectively suppresses the kink current of poly-Si TFT with anisotropic mobility in the triple-gate structure. Our experimental results show that the proposed bidirectional T-shaped triple-gate TFT can suppress the kink effect more effectively than the conventional dual-gate TFT, and L-shaped dual-gate TFT and can improve reliability under the high drain bias condition. The proposed device demonstrates that bidirectional operation is possible for integrated circuits compared with the L-shaped dual-gate structure that shows only fixed one-directional behavior. The proposed device exhibits a very low output conductance in the saturation regime, and this result indicates that higher output resistance is obtained in the proposed bidirectional T-shaped triple-gate TFT.

A novel multiple-channel structure that improves the reliability of polycrystalline silicon thin-film transistors (poly-Si TFTs) employing the sequential lateral solidification (SLS) process under high gate and drain bias stress was proposed and fabricated without any additional processes. It was successfully verified that the proposed asymmetric-spacing (AS) multiple-channel TFT effectively suppressed the threshold voltage shift by about 47% and reduced the mobility variation of the poly-Si TFT by about 3% compared with those of a conventional device by using a larger spacing in the central region of the channel area. This is possibly due to the emission of induced heat inside the device during operation. Our experimental results show that the proposed AS multiple-channel TFT has more stable electrical characteristics than the conventional-structure TFT under a high gate and drain bias condition.

For light-emitting diode (LED) excitation at 400 nm, the optical properties of a Eu2+-activated CaO–SrO–MgO–SiO2 material system were investigated. All the materials were synthesized by solid state reaction. In particular, (Ca,Sr)Mg2Si3O9:Eu2+, which has the same crystal structure as CaMgSi2O6, was found to be promising as a blue-light-emitting phosphor for near UV LED application. The luminance intensity was optimized by controlling the Eu2+ concentration and the composition of the host lattice. The ratio of calcium ions to strontium ions was a convenient parameter for adjusting the maximum excitation peak to 400 nm, which is favorable for near UV LED excitation. The highest luminance intensity of Ca1-x-y Sr y Mg2Si3O9:Eu x 2+ under 405 nm excitation was achieved at the Eu2+ concentration of x=0.01 and a Sr2+ concentration of y=0.3. The luminance intensity of (Ca,Sr)Mg2Si3O9:Eu2+ was found to be superior to that of a commercial blue-light-emitting BaMgAl10O17:Eu2+ phosphor, which is used for near-UV LED excitation.

We have investigated the electrical characteristics of short-channel p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under high gate and drain bias stress. We found that the threshold voltage of short-channel TFTs was significantly shifted in the negative direction owing to high gate and drain bias stress (ΔV TH = -2.08 V), whereas that of long-channel TFTs was rarely shifted in the negative direction (ΔV TH = -0.10 V). This negative shift of threshold voltage in the short-channel TFT may be attributed to interface state generation near the source junction and deep trap state creation near the drain junction between the poly-Si film and the gate insulator layer. It was also found that the gate-to-drain capacitance (C GD) characteristic of the stressed TFT severely stretched for the gate voltage below the flat band voltage V FB. The effects of high gate and drain bias stress are related to hot-hole-induced donor like interface state generation. The transfer characteristics of the forward and reverse modes after the high gate and drain bias stress also indicate that the interface state generation at the gate insulator/channel interface occurred near the source junction region.

A novel F-shaped triple-gate device structure, which suppresses the kink effect of polycrystalline silicon (poly-Si) thin-film transistors (TFTs), was proposed and fabricated without any additional process. The proposed poly-Si TFT exhibits a lateral grain growth in a channel, as observed in the case of TFTs fabricated by sequential lateral solidification (SLS) or CW laser lateral crystallization (CLC). The entire current flow of the proposed device was strongly affected by grain boundaries of lateral grain growth. The F-shaped triple-gate structure consisted of one channel located parallel to the lateral grain growth direction and another channel located vertically to the lateral grain growth direction. It was verified that the proposed device could effectively reduce the kink current of poly-Si TFTs using the asymmetric mobility of the F-shaped gate structure by experiment and simulation. Our experimental results showed that the proposed F-shaped triple TFT could suppress the kink effect more effectively than conventional gate TFTs and then improve reliability under hot carrier stress condition.

A high-performance p-type excimer laser annealed (ELA) polycrystalline silicon (poly-Si) thin-film transistor (TFT) was fabricated on a glass substrate. We have investigated the electrical characteristics of short-channel p-type ELA poly-Si TFTs under off-state bias stress. We have found that the threshold voltage of the short-channel TFT (L = 1.5 µm) significantly shifted in the positive direction under off-state bias stress (ΔVTH = 2.71 V), whereas the threshold voltage of long-channel TFT (L = 7 µm) barely moved in the positive direction (ΔVTH = 0.11 V). This positive shift of threshold voltage in the short-channel TFT may be attributed to electron trapping at an interface between the poly-Si film and the gate oxide layer. In addition, we have extracted the length of the drain extension from an equation of the pseudo-lightly doped drain (LDD) model to verify the existence of free hole charges induced near the drain junction. The transfer characteristics of the forward and reverse modes after the off-state bias stress indicate that the electron trapping at the gate insulator/channel interface occurred near the drain junction region. The leakage current of the ELA poly-Si TFT was also suppressed without reducing the on-current level under the off-state bias stress due to the creation of a pseudo-LDD region.