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A neural network fully implemented by memristive crossbar circuit is proposed and simulated, which can operate in parallel for the entire process. During the forward propagation, memristors in crossbar structure and a column of fixed-value resistors implement multiply-add operations. During the backward training, each memristor is tuned in conductance independently by training pulses, which implements weight/bias updating. A high recognition accuracy of 93.65% for hand-written numbers is achieved, which is comparable to that for software solution. The effects of the number of conductance states and the amplification of synaptic array circuit on the recognition accuracy are also investigated.

Complementary FET (CFET) devices have become emerging and promising candidates for continuing Moore’s law at sub-3 nm nodes owing to the area advantage of the N-P stacked structure, which markedly improves the integration of circuits. However, the introduction of vertical structure leads to severe thermal issues due to the self-heating effect, resulting in the degradation of the device and circuit performance. This paper mainly evaluates and analyzes the performance of the static random-access memory (SRAM) unit built using the CFET structure. The CFET-SRAM exhibits better performance than the conventional CMOS-SRAM in terms of access delay, even with the impact of self-heating. For the multi-fin-based CFET, although the total gate capacitance increases, the enhanced current improves the static noise margin significantly. However, as the number of channels expands, sheet-based CFET devices show more comprehensive superiority of area and performance.

In this work we present a novel convolution computing architecture based on metal oxide resistive random access memory (RRAM) to process the image data stored in the RRAM arrays. The proposed image storage architecture shows performances of better speed-device consumption efficiency compared with the previous kernel storage architecture. Further we improve the architecture for a high accuracy and low power computing by utilizing the binary storage and the series resistor. For a 28 × 28 image and 10 kernels with a size of 3 × 3, compared with the previous kernel storage approach, the newly proposed architecture shows excellent performances including: 1) almost 100% accuracy within 20% LRS variation and 90% HRS variation; 2) more than 67 times speed boost; 3) 71.4% energy saving.

In this study, we analyzed the impact of gate overlap on the performance of Schottky barrier metal–oxide–semiconductor field-effect transistors (SB MOSFETs) including the gate induced barrier lowering (GIBL) effect by two-dimensional (2D) full-band self-consistent ensemble Monte Carlo (EMC) simulation. Results show that the GIBL effect and gate overlap affect drive current significantly. The GIBL effect relieves the degradation of current drivability caused by overlap. However, the influence of scattering on the performance of SB MOSFETs is almost negligible since the electrons across the channel are nearly ballistic.

A band-to-band tunneling model including trap-assisted tunneling has been implemented in our ensemble full band Monte Carlo simulator. Four kinds of band-to-band tunneling mechanisms are taken into account. All the parameters in the band-to-band tunneling model are verified by comparing the pn junction reverse current with the experimental data. Then, gate-induced-drain-leakage currents caused by band-to-band tunneling in a 45 nm gate length n-metal–oxide–semiconductor field-effect-transistor are investigated. Results indicate that band-to-band tunneling can cause additional hot holes which becomes an important issue for the device reliability. Moreover, The gate-induced-drain-leakage currents caused by band-to-band tunneling in parallel with Si/SiO2 interface and normal to Si/SiO2 interface are compared. The influence of drain voltage on the two components of the gate-induced-drain-leakage currents is considered.

A novel ternary content addressable memory (TCAM) design based on resistive random access memory (RRAM) is presented. Each TCAM cell consists of two parallel RRAM to both store and search for ternary data. The cell size of the proposed design is 8F2, enable a ~60× cell area reduction compared with the conventional static random access memory (SRAM) based implementation. Simulation results also show that the search delay and energy consumption of the proposed design at the 64-bit word search are 2 ps and 0.18 fJ/bit/search respectively at 22 nm technology node, where significant improvements are achieved compared to previous works. The desired characteristics of RRAM for implementation of the high performance TCAM search chip are also discussed.

Degradation behaviors in the high-k/metal gate stacks of nMOSFETs are investigated by three-dimensional (3D) kinetic Monte-Carlo (KMC) simulation with multiple trap coupling. Novel microscopic mechanisms are simultaneously considered in a compound system: (1) trapping/detrapping from/to substrate/gate; (2) trapping/detrapping to other traps; (3) trap generation and recombination. Interacting traps can contribute to random telegraph noise (RTN), bias temperature instability (BTI), and trap-assisted tunneling (TAT). Simulation results show that trap interaction induces higher probability and greater complexity in trapping/detrapping processes and greatly affects the characteristics of RTN and BTI. Different types of trap distribution cause largely different behaviors of RTN, BTI, and TAT. TAT currents caused by multiple trap coupling are sensitive to the gate voltage. Moreover, trap generation and recombination have great effects on the degradation of HfO2-based nMOSFETs under a large stress.

The traditional Boolean computing paradigm based on the von Neumann architecture is facing great challenges for future information technology applications such as big data, the Internet of Things (IoT), and wearable devices, due to the limited processing capability issues such as binary data storage and computing, non-parallel data processing, and the buses requirement between memory units and logic units. The brain-inspired neuromorphic computing paradigm is believed to be one of the promising solutions for realizing more complex functions with a lower cost. To perform such brain-inspired computing with a low cost and low power consumption, novel devices for use as electronic synapses are needed. Metal oxide resistive random access memory (ReRAM) devices have emerged as the leading candidate for electronic synapses. This paper comprehensively addresses the recent work on the design and optimization of metal oxide ReRAM-based synaptic devices. A performance enhancement methodology and optimized operation scheme to achieve analog resistive switching and low-energy training behavior are provided. A three-dimensional vertical synapse network architecture is proposed for high-density integration and low-cost fabrication. The impacts of the ReRAM synaptic device features on the performances of neuromorphic systems are also discussed on the basis of a constructed neuromorphic visual system with a pattern recognition function. Possible solutions to achieve the high recognition accuracy and efficiency of neuromorphic systems are presented.

In this work, the strain effect on monolayer MoS2 field effect transistors is investigated by density functional (DFT) calculation and quantum transport simulation. DFT calculation reveals that the tensile strain decreases the effective mass, while compressive strain increases the effective mass. However, ballistic quantum transport simulation shows that a smaller effective mass does not always result in better performance for a 5 nm gate length transistor. This is because for field effect transistors in the ultimate scaling region, the suppression of off-state tunneling current is the greatest concern in device design. The effect of scattering is considered by a simple approach and is shown to have a stronger impact on the intrinsic delay for the 10 nm gate length transistor.

We explore the use of strain and heterostructure design based on physical modeling to enhance the hole mobility in ultrathin body InxGa1−xSb-based p-channel MOSFETs. The band structure under quantum confinement is calculated by solving the six-band k p Schrodinger and Poisson equations self-consistently. Hole mobility is modeled by the Kubo–Greenwood formula accounting for acoustic and optical phonons, polar optical phonons, surface roughness, and alloy scattering mechanisms. Physical models are calibrated with experimental data. Our results suggest that hole mobility in InxGa1−xSb-based devices increases with increasing InSb mole fraction x, especially under biaxial compressive strain. Mobility markedly deteriorates with the scaling down of body thickness in both unstrained and strained cases. Moreover, an insert of a very thin cap layer with a wide bandgap is helpful to enhance hole mobility. Therefore, greater mobility enhancements are achieved by strained heterostructure optimization.

The strain effect on the electronic properties of bilayer tungsten disulfide (WS2) is investigated by density functional theory (DFT). It is found that the band gap and carrier effective masses of AA and AB stacking bilayer WS2 decrease with increasing tensile strain. However, their band gap first increases under small compressive strain and then decreases with large compressive strain applied. These results can be explained by the interplay between the projected density of states contributed by the p-orbital of sulfur (S) atoms and those contributed by the d-orbital of tungsten (W) atoms. To measure this interaction quantitatively, a parameter N is proposed in our work. This work could serve as a guideline for the future manipulation of the electronic properties of WS2.

In this work, three dimensional technology computer-aided design (TCAD) simulations are performed to investigate the impact of random discrete dopant (RDD) including extension induced fluctuation in 14 nm silicon-on-insulator (SOI) gate–source/drain (G–S/D) underlap fin field effect transistor (FinFET). To fully understand the RDD impact in extension, RDD effect is evaluated in channel and extension separately and together. The statistical variability of FinFET performance parameters including threshold voltage (V th), subthreshold slope (SS), drain induced barrier lowering (DIBL), drive current (I on), and leakage current (I off) are analyzed. The results indicate that RDD in extension can lead to substantial variability, especially for SS, DIBL, and I on and should be taken into account together with that in channel to get an accurate estimation on RDF. Meanwhile, higher doping concentration of extension region is suggested from the perspective of overall variability control.

In this work, we evaluate the program/erase/retention performance of a novel TaN/Al2O3/TiO2/HfO2/SiO2/Si (TATHOS) charge trapping memory (CTM) device with the stacked HfO2/SiO2 tunneling layer and TiO2 charge trapping layer by our developed simulator, which has included the critical mechanisms in CTM and has been verified with the experiment data. With various gate dielectric layer's thicknesses and materials, bias voltages and temperatures, the novel structure device's performance are studied and compared to some conventional devices. It can been seen that with appropriate design for the stack tunneling layer and TiO2 choice for the charge trapping layer, significantly improved program/erase speed and retention characteristics could be achieved. It can be a useful tool to optimize the performance of CTM with the gate layer materials' choice and design.

Large switching current is a great challenge for scaling down of the oxide-based resistive random access memory devices to realize high density and low power memory array. In this paper, large operation current caused by the current overshoot effect during forming process is investigated using a stochastic simulator based on the percolation theory. The electrical characteristic of forming process is simulated and compared with the experimental data. Our simulation demonstrates that the current overshoot effect results in a stronger conductive filament during forming process, which will cause a larger operation current in subsequent switching cycle. Furthermore, our simulation results reveal that low sweeping rate, high ambient temperature, high doping concentration and high pre-exist oxygen vacancies (VO) concentration are beneficial to the control of conductive filament evolution and the suppression of the current overshoot effect, which is critical for low reset current and low operation power resistive-switching random access memory (RRAM).

Using full three-dimensional (3D) technology computer-aided design (TCAD) simulations, we present a comprehensive statistical study on the random discrete dopant (RDD) induced variability in state-of-the-art intrinsic channel trigate MOSFETs. This paper is focused on the RDD variability sources that are introduced by dopant diffusion from highly doped source/drain (S/D) regions into the undoped channel region, which is referred to as junction nonabruptness (JNA). By considering a realistic lateral doping profile in the channel and evaluating the impact of JNA on the variability of performance parameters such as threshold voltage (V th), subthreshold slope (SS), drain-induced barrier lowering (DIBL), on current (I on), and off current (I off), we show that the effect of JNA can lead to substantial device variations. The nonnegligible influence of JNA puts limitations on device scaling, which is also investigated in this paper.

We developed a comprehensive simulation program of phase change memory (PCM) including the electrical, thermal, phase change and percolation model. The set, reset and retention behavior for a typical thin film phase change material (GST) are simulated and evaluated. Both the resistance evaluation and the micro phase change process are simulated that can help to understand of the phase change physical mechanism. The influence of pre-existing grains on the retention is evaluated considering the pre-existing grains' amount and its distribution.

The effects of intrinsic parameter fluctuations, including line-edge-roughness (LER), silicon-body thickness variation (STV) and work-function variation (WFV), in 20-nm-gate variable-γ silicon-on-thin-box (SOTB) metal oxide semiconductor field effect transistors (MOSFETs) have been investigated and compared with those of the conventional SOTB. Results show that the variable-γ SOTB offers not only an enhanced I on but also a reduced I on fluctuation with a small increase in the active-state I off fluctuation. The V th-roll-off value in the variable-γ SOTB can be reduced by adopting a reverse-biased side gate to optimize the short channel effect, but the variability of the DIBL effect is enlarged. It is expected that a thinner silicon body can be used to reduce the dominant variability sources.

Various Si1-x Ge x shell strains induced by changing the thickness or tuning the Ge and Si contents as well as by modulating the valence band structure and hole transport characteristics of core/shell nanowire field effect transistors (FETs) have been calculated. As Si1-x Ge x shell thickness increases, the strained valence subbands shift upwards and warp markedly. Most of the corresponding hole effective masses of the top five subbands decrease. Meanwhile, the hole mobility of the Ge(110) nanowire increases with increasing shell thickness. As the Ge concentration in the Si1-x Ge x shell decreases, the strained valence subbands and hole mobility show similar shifts. As a result, our calculation indicates the possibility of improving the nanowire performance of heterostructure nanowire FETs.

In this paper, TiN/ZrO2/Pt sandwiched resistive switching memory devices were fabricated. The effect of set current compliance on the resistive switching behaviors in TiN/ZrO2/Pt memory device was studied. The different dependence of low resistance state on the set current compliance were observed under the different magnitudes of set current compliance: 1) the average read current was linearly dependent on the set current compliance in the magnitude of low set current compliance; 2) then a weaker dependence of the average read current on the set current compliance was observed in the magnitude of higher set current compliance; 3) when the current compliance is high enough, the unipolar resistive switching behaviors instead of the bipolar resistive switching was shown. A physical model based on oxygen vacancy conducting filamentary paths is proposed to explain the effect of set current compliance on the resistive switching behaviors in TiN/ZrO2/Pt memory device.

Three-dimensional (3D) statistical simulation is presented to propose using triple-gate (TG) fin field effect transistors (FinFETs) with optimized fin-thickness (Tsi) to reduce the fin line edge roughness (LER) effect both in the device and circuit level. The results show that ultrathin fin will lead to intolerable parameter fluctuations in 20 nm double-gate (DG) FinFETs and FinFETs static random access memory (SRAM). Increasing Tsi can alleviate fin LER effect, but in the meantime it will exacerbate the short channel effect (SCE). TG structure can strengthen the gate controllability over the channel, thus, can suppress SCE and reduce LER effect as well. Adopting TG structure can relax the constraint of fin-thickness to half the gate length.

The properties of ferroelectric nanodomains in LiNbO3 crystals were investigated using scanning force microscopy. In particular, we found differences in the domain shape, domain-wall sharpness, and lateral growth rate of domains in near-stoichiometric and congruent LiNbO3 crystals. In the near-stoichiometric LiNbO3 crystal, the domain dots are hexagonal and linear domains with smooth walls can be engineered parallel to one of the crystallographic Y-axes. The shape of the linear domains engineered at an angle to the crystallographic Y-axis changes when a small bias is applied during scanning, and various domain shapes are obtained after being stabilized by scanning. However, in the congruent LiNbO3 crystal, the domain dots are roughly circular and there is no change in the shape of the linear domains, which have rough domain walls. The lateral growth rate of domains in the congruent LiNbO3 crystal is smaller than that in the near-stoichiometric LiNbO3 crystal.

Germanium metal-oxide-semiconductor field-effect transistors (MOSFETs) have attracted tremendous attention due to the high carrier mobility especially in the low-field. Compared to Si, in bulk germanium the velocity would saturate at a lower field with a lower saturation velocity. Thus the scaling behavior of germanium MOSFET with gate length in nano-scale is very important. In this work, characteristics of both n- and p-channel germanium on Insulator (GOI) MOSFETs with channel length (L ch) ranging from 20 nm to 130 nm are simulated by 2D self-consistent full-band Monte Carlo device simulator to investigate the scaling properties. The results indicate that both for n and p channel GOI MOSFETs have favorable scaling properties in nano-scale due to the non-stationary transport near source side especially for p channel device. But the surface roughness scattering is a critical issue that might suppress the non-stationary transport. Short channel effect (SCE) is serious in GOI devices and much thinner Germanium layer have to use to optimize the performance.