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For developing p-GaN gate-based enhancement-mode AlGaN/GaN high-electron-mobility transistors, the removal of the p-GaN layer around the gate region is demonstrated by photo-electrochemical etching. The etching behavior of p-GaN/AlGaN/GaN heterostructures along with p-GaN/u-GaN reference samples is investigated in acidic H2SO4/H3PO4 electrolyte solution. The strong oxidant sulfate radical SO 4 − ∗ formed by H2SO4 stimulates the etching process by either extracting excess electrons from the valence band or providing supplementary holes in the valence band. By optimizing the etching parameters, an average etching rate of 0.27 nm/min with a surface roughness of 2.3 nm is achieved for removing p-GaN from the AlGaN/GaN structure. The etching dynamics of the heterostructure are attributed to the valence-band offset ΔEv caused by band discontinuity at the p-GaN/AlGaN interface. Under positive anodic bias, the etching process is also controlled by local charge transport between p-GaN and the two-dimensional electron gas channel due to a reduced barrier height. [ABSTRACT FROM AUTHOR]

The dark current mechanism of extended wavelength InxGa1-xAs photo-detectors is still a debated issue. In this paper, the deep-level transient spectroscopy (DLTS) and dark current characteristics of InxGa1-xAs/InP detectors are investigated. Using trap parameters obtained from DLTS measurement, the device simulations of current-voltage characteristics are carried out by Silvaco Altas. The results reveal that the dark current at the low reverse bias voltage is associated with deep level trap induced trap assisted tunneling and Shockley-Read-Hall generation mechanism. The reduction of the deep level trap concentration in InxGa1-xAs absorption layer could dramatically suppress the dark current near zero bias in extended wavelength InxGa1-xAs/InP detectors. [ABSTRACT FROM AUTHOR]

The physical mechanism of VT degradations under negative bias temperature stress below room temperature has been studied for SiO2 and plasma nitrided oxide (PNO-based) pMOSFETs. It is found that VT degradations in both devices exhibit strong dependence on the electric field and temperature. The analysis shows that this strong dependence follows multi-phonon field-assisted tunneling theory, which indicates the inelastic hole trapping mechanism in the low temperature negative bias temperature instability (NBTI). On the other hand, by applying a low temperature sweeping technique, the energy distribution of these NBTI-induced hole traps below room temperature is indentified. The energy distribution of hole traps has two obvious peaks, one in the lower and one in the upper half of the silicon band gap. Both peaks gradually develop with increasing the stress time and temperature. We attempt to compare the energy profile for SiO2 and PNO devices to identify the trap precursors in NBTI below room temperature. [ABSTRACT FROM AUTHOR]