Search

We show experimentally that, in the same Si devices, we can demonstrate multiple two-gate pumping modes but not single-gate mode. We contrast this with GaAs devices, which do show single-gate pumping at a high yield. We propose four mechanisms to explain the lack of plateaus in the Si devices in single-gate ratchet mode: operating the dot with a large number of electrons, a large ratio between the change in electrochemical potential energy and the change in the energy of the barrier (plunger-to-barrier ratio, Δptb) compared to the charging energy (Δptb/EC), nonlinear tunnel barriers, and phase offset leading to nonequilibrium heating. Our analysis shows that each of these could contribute to the lack of plateaus in single-gate ratchet pumping on Si devices but allow two-gate pumping methods to work with robust plateaus. It is easier for GaAs pumps to avoid these failure mechanisms due to their different architectures and cleaner gate turnoff curves. We propose several methods to reduce these sources of error, including reducing cross capacitances between gates. These recommendations may prove useful to other researchers in producing more robust, higher yield single-gate ratchet pumps. [ABSTRACT FROM AUTHOR]

We have measured the low-frequency time instability known as charge offset drift of Si/SiO 2 single electron devices (SEDs) with and without an overall poly-Si top gate. We find that SEDs with a poly-Si top gate have significantly less charge offset drift, exhibiting fewer isolated jumps and a factor of two reduction in fluctuations about a stable mean value. The observed reduction can be accounted for by the electrostatic reduction in the mutual capacitance C m between defects and the quantum dot and increase in the total defect capacitance C d due to the top gate. These results depart from the prominent interpretation that the level of charge offset drift in SEDs is determined by the intrinsic material properties, forcing consideration of the device design as well. We expect these results to be of importance in developing SEDs for applications from quantum information to metrology or wherever charge noise or integrability of devices is a challenge. [ABSTRACT FROM AUTHOR]

Pauli-spin blockade (PSB) is a transport phenomenon in double quantum dots that allows for a type of spin to charge conversion often used to probe fundamental physics such as spin relaxation and singlet-triplet coupling. In this paper, we theoretically explore Pauli-spin blockade as a function of magnetic field B applied parallel to the substrate. In the well-studied low magnetic field regime, where PSB occurs in the forward (1, 1) → (0, 2) tunneling direction, we highlight some aspects of PSB that are not discussed in detail in existing literature, including the change in size of both bias triangles measured in the forward and reverse biasing directions as a function of B. At higher fields, we predict a crossover to "reverse PSB" in which current is blockaded in the reverse direction due to the occupation of a spin singlet as opposed to the traditional triplet blockade that occurs at low fields. The onset of reverse PSB coincides with the development of a tail like feature in the measured bias triangles and occurs when the Zeeman energy of the polarized triplet equals the exchange energy in the (0, 2) charge configuration. In Si quantum dots, these fields are experimentally accessible; thus, this work suggests a way to observe a crossover in magnetic field to qualitatively different behavior. [ABSTRACT FROM AUTHOR]

We have measured the low-frequency time instability known as charge offset drift of Si/SiO 2 single electron devices (SEDs) with and without an overall poly-Si top gate. We find that SEDs with a poly-Si top gate have significantly less charge offset drift, exhibiting fewer isolated jumps and a factor of two reduction in fluctuations about a stable mean value. The observed reduction can be accounted for by the electrostatic reduction in the mutual capacitance C m between defects and the quantum dot, and increase in the total defect capacitance C d due to the top gate. These results depart from the prominent interpretation that the level of charge offset drift in SEDs is determined by the intrinsic material properties, forcing consideration of the device design as well. We expect these results to be of importance in developing SEDs for applications from quantum information to metrology or wherever charge noise or integrability of devices is a challenge.