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Application-Specific ICs (ASIC) are manufactured in bulk for a long time. In this paper, an approach to High-Speed Application-Independent IC (HS-AIIC) design is discussed. A resolution-selective (RS) and resolution-adaptive (RA) 8-bit Flash ADC are designed for use in various high-speed applications. With the choice of resolution, one can work with the trade-off between speed, power consumption, and resolution for a particular application. The proposed resolution selection algorithm can be implemented for any set of resolutions for a flash ADC design. Further, an adaptive block is added to make the ADC design adaptive in nature so that we do not have to select a particular resolution manually. The proposed design entrusts on saving manufacturing cost and increases the functionality of ADC on a single chip. Proposed resolution adaptive 8-bit flash ADC design dissipates 512 mW of power with an ENOB of 7.56 bits and SNDR of 46.27 dB for 1 GHz sampling clock pulse. [ABSTRACT FROM AUTHOR]

Emergent wireless communication standards, which are employed in different transmission environments, support various modulation schemes. High-order constellations are targeted to achieve high bandwidth efficiency. However, the complexity of the symbol-by-symbol Maximum A Posteriori (MAP) algorithm increases dramatically for these high-order modulation schemes. In order to reduce the hardware complexity, the suboptimal Max-Log-MAP, which is the direct transformation of the MAP algorithm into logarithmic domain, is alternatively implemented. In the literature, a great deal of research effort has been invested into Max-Log-MAP demapping. Several simplifications are presented to meet with specific constellations. In addition, the hardware implementations dedicated for Max-Log-MAP demapping vary greatly in terms of design choices, supported flexibility and performance criteria, making them a challenge to compare. This paper explores the published Max-Log-MAP algorithm simplifications and existing hardware demapper designs and presents an extensive review of the current literature. In-depth comparisons are drawn amongst the designs and different key performance characteristics are described, namely, achieved throughput, hardware resource requirements and flexibility. This survey should facilitate fair comparisons of future designs, as well as opportunities for improving the design of Max-Log-MAP demappers. [ABSTRACT FROM AUTHOR]