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Testing modern integrated circuit (IC) is challenging with introduction of System-on Chip (SOC). Enormous test pattern count is required to authenticate the IC which inflates power consumption. Henceforth, it is mandatory to incorporate power minimization techniques at circuit design phase. Optimizing test patterns is one such effective technique that curtails test power without altering circuit design. In this paper, a new test pattern reordering algorithm is proposed based on Recurrent Neural Network. Hopfield Neural Network (HNN) constitutes an optimized solution for solving traveling salesman problem (TSP). Since, test pattern reordering can be interpreted as TSP, optimized test pattern order is attained with HNN. Energy function of this algorithm falls into local minimum, so to eradicate this issue, the algorithm is modified. Test patterns are reordered with minimal hamming distance among consecutive test patterns. The proposed algorithm is implemented in ISCAS'89 Sequential Benchmark circuits. Experimental results prove that significant reduction in transition count is accomplished with proposed algorithm without compromising fault coverage. [ABSTRACT FROM AUTHOR]

Feature extraction and matching are the basic procedures of the so-called Visual Odometer (VO), Simultaneous Localization and Mapping (SLAM) and many other image processing algorithms. Oriented features from accelerated segment test (FAST) and rotated binary robust independent elementary features (ORB) algorithm are widely used since they are computationally faster. In this paper, we proposed a method to generate a value for a feature, the value is called signature. In the matching step, we only compute Hamming distances of descriptors with the same signatures. Hence, the matching time is shortened. Compared with the original ORB algorithm, features to be matched dropped 69.63% on TUM datasets and 85.7% on VGG datasets by adopting our strategy. In addition, the precision is above 85% on both VGG and TUM datasets. We design a customized hardware architecture for ORB feature extraction and matching based on the proposed method. The hardware structure is implemented on Xilinx ZCU102 evaluation board. The clock frequency is set to 150 MHz. Our Field Programmable Gate Arrays (FPGA) system achieves 193 fps on 1 2 8 0 × 7 2 0 images with 1984 features on average and 314 fps on 6 4 0 × 4 8 0 images with 700 features on average, which is more efficient compared to the state-of-the-art works. [ABSTRACT FROM AUTHOR]

Effective resistance to intellectual property (IP) piracy, overproduction and reverse engineering are becoming more and more necessary in the integrated circuit (IC) supply chain. To protect the hardware, the obfuscation methodology hides the original function by adding a large number of redundant states. However, existing hardware obfuscation approaches have hardware overhead and efficiency of obfuscation limitations. This paper proposed a novel methodology for IP security using the minimum spanning tree finite state machine (MST-FSM) obfuscation. In the minimum spanning tree (MST) algorithm, the Hamming distance defines the cost of obfuscated states. The Kruskal algorithm optimizes the connection relationship of obfuscated states by computing the Hamming distance of the MST-FSM. The proposed MST-FSM is automatically generated and embedded in the hardware IP with the self-building program. Finally, the MST-FSM is applied on the itc99 benchmark circuits and encryption standard IP cores. Compared with other state-of-the-arts, the obfuscation potency is improved by 3.57%, and the average hardware cost is decreased by about 6.01%. [ABSTRACT FROM AUTHOR]