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This paper presents the realization of binary and floating-point comparators on FPGA. The implementation is done by exploiting the primitive instantiation of FPGA resources which has enabled a significant improvement in resource utilization in terms of Look-Up Table (LUT) usage and overall combinational path delay when compared to the conventional inference approach. The comparator architectures are implemented using Vivado 2020.1 and ISE Design Suite 14.7 environment on multiple Xilinx FPGA platforms and are compared with the existing designs. The results indicate an improvement of 33.33% and 45.45% in LUT utilization, 14.41% and 30.73% in delay for 32-bit and 64-bit binary comparators respectively, compared to the existing architectures. The proposed floating-point comparator requires 88.57% and 285.29% lesser LUTs for single precision and double precision representation respectively, compared to the existing design. [ABSTRACT FROM AUTHOR]

This paper presents a scalable Fully-digital differential analog voltage comparator designed in Semi-Conductor Laboratory (SCL) 180 nm complementary metal-oxide semiconductor technology. The proposed design is based on a digital design approach and is easily configurable to lower technology nodes. This design methodology makes the circuit less sensitive to process variations and takes fewer design efforts suitable for Systems-on-a-Chips (SOCs) application. The proposed circuit is designed and simulated in Cadence Virtuoso Analog Design Environment at the supply voltage ranging from 1 V to 1.8 V. The fully-digital analog voltage comparator has been synthesized using Synopsys Design Vision and auto-placed & auto-routed using Synopsys IC Compiler. This proposed comparator has a resolution of up to 7-bit at a supply voltage of 1.8 V and a worst-case operating frequency of about 750 MHz at the TT corner. The obtained value of the offset voltage and delay is 0.55 mV and 0.72 ns, respectively. The simulated results have shown that the power dissipation of the proposed scalable analog voltage comparator is 1 5 0 μ W @ 1 V and 3 1 2 μ W @ 1. 8 V supply voltage, respectively. Also, the RC extracted post-layout simulations have been implemented to verify the performance, which does not affect the results much. [ABSTRACT FROM AUTHOR]

Reduced voltage head room availability for input signal swing is one of the major bottlenecks in the design of circuits operating with low supply voltages which attracts investigations leading to improvement in the input signal dynamic range of such circuits. Employing bulk-driven MOSFETs (BDMOS) at the input section of the circuit is a popular technique used for increasing the input dynamic range, but the smaller bulk transconductance of the bulk-driven MOSFET degrades the performance of the circuit in comparison with that of a conventional gate-driven counterpart. A double tail voltage comparator employing BDMOS technique offering rail-to-rail input dynamic range and capable of operating at sub-1 V power supply is presented in this paper. A transconductance improvement scheme is employed for the first time in the literature for a voltage comparator to overcome the major drawbacks associated with the reduced bulk transconductance of BDMOS input transistors and double tail topology permits low voltage operation. The performance parameters of the proposed voltage comparator are comparable to that of conventional gate-driven comparators, with an additional advantage of rail-to-rail input dynamic range. Pre-layout and post-layout simulations were performed in Cadence Virtuoso suite with gpdk 90 nm library at power supply as low as 0.6 V. The worst case delay of the proposed circuit is 0.71 ns and the worst case power consumption of the circuit is 15 uW. The circuit consumes a silicon area of 33 μm × 46 μm. An analytical model of the transconductance enhancement technique and delay of the proposed comparator are also presented. [ABSTRACT FROM AUTHOR]

Single-slope analog-to-digital converter (SS ADC) and time-to-digital converter (TDC) architectures in their high-speed or high-resolution status tend to either have high-power consumption or occupy large area. However, using the hybrid structure of these two, although synchronizing them might be a limiting factor, can solve the area and power consumption issues. In this paper, a 4-bit SS ADC is combined with a 4-bit TDC. Moreover, a new low-powered continuous-time comparator architecture is designed to adjust its current based on not only the inputs amplitude but also their proximity near the flip point. In addition, a novel delay correction technique is utilized to resolve its nonlinear propagation delay. The presented technique reduces 90% nonlinearity of the comparator's propagation delay and decreases its delay variation to 450 ps. Using TSMC CMOS 130 nm technology with a sampling frequency of 5.88 MHz, the simulation result illustrates 788 μ W power consumption with the master clock frequency of 100 MHz while an integral nonlinearity (INL) of − 1.41–+0.76 LSB and a differential nonlinearity (DNL) of − 1.05–+0.05 LSB is achieved in 625 ps resolution. Finally, figure-of-merit (FoM) depicts 31.2 fJ/conv. step. The presented converter can be used in CMOS image sensors and multi-resolution applications. [ABSTRACT FROM AUTHOR]

In this paper, a comparator and an operational amplifier considered as essential components, constituting a 10-bit 50-MHz pipeline Analog-to-Digital Converter for Wireless Local Area Network (WLAN) applications, are described and designed. All post-layout and Monte-Carlo simulations, using a 0.35 μ m CMOS AMS process technology with 3. 3 V supply voltage and an input common-mode range of 1. 1 5 – 2. 1 5 V, are achieved. An improved clocked comparator with a dynamic latch, based on a switched capacitor network, using the current reuse technique for slew rate enhancement and positive feedback for offset voltage compensation, is presented. The operational amplifier, consisting of a fully differential folded cascode operational transconductance amplifier, providing high-gain and good stability, is exhibited. A new frequency compensation technique, based on active resistors, is used to improve amplifier phase-margin. The Monte-Carlo performance results of the designed clocked comparator provide an offset voltage of 3 2. 3 2 mV with 2. 4 9 mV 3 σ deviation, a slew rate of 8. 2 9 V/ns with 0. 4 5 V/ns 3 σ deviation, and a propagation delay of 4. 1 6 ns with 0. 1 5 ns 3 σ deviation. Monte-Carlo performance results of the designed operational amplifier provide a phase-margin of 6 3. 0 1 ∘ , and a high-gain of 7 9. 2 2 dB with 1. 9 2 ∘ and 4. 8 6 dB 3 σ , respectively, by using 1 pF load capacitance. [ABSTRACT FROM AUTHOR]

The need of energy-efficient, high-speed, and low-offset analog-to-digital converters is forcing to design the dynamic latch comparators to enhance the speed and energy efficiency with minimum offset. This paper presents a novel double tail dynamic latch comparator using bulk-driven process and common-gate (CG) amplifier in amplification stage. The gain of amplification stage is enhanced using GACOBA load in which gain is controlled by bulk amplification through CG amplifier. It results in remarkable enhancement in regeneration speed and reduction in power consumption. The analytical expressions of delay and offset due to mismatch are also derived. These derivations explore the key contributors to reduce the delay and offset of proposed comparator. The outcomes are verified in CADENCE SPECTRE at 45-nm CMOS process technology through various simulations and Monte-Carlo analysis at different process corners. The post-layout analysis validates the simulation results. The proposed comparator is 93% more energy-efficient and lessens more than 84% delay in comparison of conventional design. The 1– σ input offset voltage and average input voltage error due to kickback noise are 2.48 mV and 0.824 μ V, respectively at 0.8 V power supply with 34.32 μ m2 active area. [ABSTRACT FROM AUTHOR]

This paper presents a linearity improved 10-bit 120-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with high-speed and low-noise dynamic comparator. A gate cross-coupled technique is introduced in boost sampling switch, the clock feedthrough effect is compensated without extra auxiliary switch and the linearity of sampling switch is enhanced. Further, substrate voltage boost technique is proposed, the absolute values of threshold voltage and equivalent impedances of MOSFETs are both depressed. Consequently, the delay of comparator is also reduced. Moreover, the reduction of threshold voltages for input MOSFETs could bring higher transconductance and lower equivalent input noise. To demonstrate the proposed techniques, a design of SAR ADC is fabricated in 65-nm CMOS technology, consuming 1.5 mW from 1 V power supply with a SNDR > 5 5. 8 dB and SFDR > 6 6. 5 dB. The proposed ADC core occupies an active area of 0.021 mm2, and the corresponding FoM is 24.4 fJ/conversion-step with Nyquist frequency. [ABSTRACT FROM AUTHOR]

In this paper, we present a CMOS full-wave rectifier with comparator-controlled switches for transmission of wireless power in implantable medical devices. It uses MOS transistors as low loss switches to provide high power conversion efficiency (PCE). The proposed fast comparator circuit, by controlling the switches in the rectifier, reduces the reverse leakage current in the negative cycle and increases the conduction time in the positive cycle so that more current flows into the output load and optimizes the rectifier power efficiency. The designed comparator does not require constant voltage source for its function and it is self-biased. The proposed rectifier is implemented using 0.18 μ m CMOS technology and provides 1.195 V output DC voltage with a 190 Ω load resistance and AC input signal with the frequency of 13.56 MHz and peak-to-peak amplitude of 1.36 V. Under these conditions, PCE and voltage conversion efficiency (VCE) values are 85.5% and 88%, respectively. The peak PCE and VCE increase with a decrease in operation frequency and dimensions of transistors are optimized using multiple simulations for intended frequency. [ABSTRACT FROM AUTHOR]

In this paper, a 10-bit 0.5 V 100 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a new fully dynamic rail-to-rail comparator is presented. The proposed comparator enhances the input signal range to the rail-to-rail mode, and hence, improves the signal-to-noise ratio (SNR) of the ADC in low supply voltages. The effect of the latch offset voltage is reduced by providing a higher voltage gain in the regenerative latch. To reduce the ADC power consumption further, the binary-weighted capacitive array with an attenuation capacitor (BWA) is employed as the digital-to-analog converter (DAC) in this design. The ADC is designed and simulated in a 90 nm CMOS process with a single 0.5 V power supply. Spectre simulation results show that the average power consumption of the proposed ADC is about 400 nW and the peak signal-to-noise plus distortion ratio (SNDR) is 56 dB. By considering 10% increase in total ADC power consumption due to the parasitics and a loss of 0.22 LSB in ENOB due to the DAC capacitors mismatch, the achieved figure of merit (FoM) is 11.4 fJ/conversion-step. [ABSTRACT FROM AUTHOR]