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Electronic packages are multimaterial structures. Their reliability is a major concern for the electronic industry and therefore widely studied. Apart from the electrical performance, the mechanical stability also needs attention. A dreaded failure cause is delamination. Therefore it is interesting to have a modeling tool, which can provide information on possible delamination risks. In this paper, a short overview of existing appropriate analyzing techniques is presented, focusing on the fracture-mechanics approach. The implementation of the method using energy release rate components is discussed. However, as in all modeling applications, the need for 'critical material data' is also at hand. Therefore, the shear test is demonstrated to serve as a characterization tool The Si-BCB interface is applied as test-case. In order to obtain the critical material data for this interface, a set of experiments is designed and performed. Due to the brittle failure observed in the experiments, only information about the onset of the delamination is obtained, leading to a crack extension locus. By comparing the experimental results and the numerical finite element results, an estimation on this crack extension locus (in the [G.sub.1]-[G.sub.2] plane) can be made. This information can be used in later calculations on the reliability of components including Si-BCB interfaces. [DOI: 10.1115/1.4000209]

An analytical model is derived for the calculation of thermo-mechanical induced stresses in area array flip chip assemblies. This analytical model is based on structural mechanics and has the ability to characterize the nature and to estimate the magnitude of the induced stresses. The extension of this model compared to existing procedures is its applicability to area array systems, which behave significantly different from peripheral assemblies. The model is compared to finite element simulations. The model calculates accurately the forces and bending moments acting on the flip chip connections. The transformation of these forces and moments into stresses is less accurate as the model does not include stress concentrations near the corners. The model simulates very well the different parameter trends such as chip size and is therefore well suited for understanding parameter sensitivity studies.

Finite element modeling is widely used for estimating the solder joint reliability of electronic packages. In this study, the electronic package is a CSP mounted on a printed circuit board (PCB) using an area array of solder joints varying from 5X4 up to 7X7. An empirical model for estimating the reliability of CSP solder joints is derived by correlating the simulated strains to thermal cycling results for 20 different sample configurations. This empirical model translates the inelastic strains calculated by nonlinear three-dimensional (3D) finite element simulations into a reliability estimation ([N.sub.50%] or [N.sub.100 ppm]). By comparing with the results of reliability tests, it can be concluded that this model is accurate and consistent for analyzing the effect of solder joint geometry. Afterwards, parameter sensitivity analysis was conducted by integrating a design of experiment (DOE) analysis with the reliable solder fatigue prediction models, following the method of simulation-based optimization. Several parameters are analyzed: the PCB parameters (elastic modulus, coefficient of thermal expansion, thickness), the chip dimensions (area array configuration), and the parameters defining the solder joint geometry (substrate and chip pad diameter, solder volume). The first study analyzes how the solder joint geometry influences the CSP reliability. A second study is a tolerance analysis for six parameters. These parameters can have a tolerance (=accuracy) of their nominal value, and it is shown that these small tolerances can have a significant influence on the solder joint reliability.

Electronic packages are multimaterial structures. Their reliability is a major concern for the electronic industry and therefore widely studied. Apart from the electrical performance, the mechanical stability also needs attention. A dreaded failure cause is delamination. Therefore it is interesting to have a modeling tool, which can provide information on possible delamination risks. In this paper a short overview of existing appropriate analyzing techniques is presented, focusing on the fracture-mechanics approach. The implementation of the method using energy release rate components is discussed. However as in all modeling applications, the need for "critical material data" is also at hand. Therefore, the shear test is demonstrated to serve as a characterization tool. The Si-BCB interface is applied as test-case. In order to obtain the critical material data for this interface, a set of experiments is designed and performed. Due to the brittle failure observed in the experiments, only information about the onset of the delamination is obtained, leading to a crack extension locus. By comparing the experimental results and the numerical finite element results, an estimation on this crack extension locus (in the G1-G2 plane) can be made. This information can be used in later calculations on the reliability of components including Si-BCB interfaces. [ABSTRACT FROM AUTHOR]