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This paper deals with the thermal management of a TBGA chip carrier package. In TBGA packages the backside of the chip is available for heat sink or heat spreader (cover plate) attach. By attaching a heat sink directly to the chip and using a thin layer of high thermal conductivity adhesive, a very low internal thermal resistance can be achieved. The package is attached to an organic card and placed vertically in a channel. A three-dimensional conjugate heat transfer model is used, accounting for conduction and radiation in the package and card and convection in the surrounding air. A simplified turbulence model is developed to predict temperatures in the low Re turbulence regime. A parametric study is performed to evaluate the effects of card design, air velocities, interconnect thermal conductivities and thermal radiation on the chip junction temperatures. An experimental study was also conducted to verify the model. Even though the geometry is highly complex due to the multilayer construction of the module and the card, agreement between the model and the experimental measurement is excellent. It was shown that radiation heat transfer can be an equally significant mode as convection in the natural convection regime. [S1043-7398(00)01302-5]

This paper presents a solution methodology for the optimal placement of convectively and conductively air-cooled electronic components on planar printed wiring boards considering thermal and electrical/cost design objectives. The methodology combines the use of a heat transfer solver for the prediction of the temperature distribution among the electronic components and a genetic algorithm for the adaptive search of optimal or near optimal solutions and a multiobjective optimization strategy (Pareto optimization and multiattribute utility analysis). After proper validation of the elements of the solution methodology (heat transfer solver/genetic algorithm) in isolation, the methodology under consideration is tested using a placement problem (case study) that considers as optimization criteria the minimization of an estimate of the failure rate of the system of components due to thermal overheating (via an Arrhenius relation) and the minimization of the total wiring length given some interconnectivity requirements. Results corresponding to the case study are presented and discussed for both Pareto optimization and multiattribute utility analysis. [S1043-7398(00)00801-X]

Wearable computers are rugged, portable computers that can be comfortably worn on the body and easily operated for maintenance applications. The recently developed process of Shape Deposition Manufacturing has created the opportunity to embed the electronics of wearable computers in a polymer composite substrate. As both a protective outer case and a conductive heat dissipating medium, the substrate satisfies two basic constraints of wearable computer design: ruggedness and cooling efficiency. One such application of embedded electronics is the VuMan3R, a wearable computer designed and manufactured at Carnegie Mellon University for aircraft maintenance. This paper combines finite element numerical simulations, physical experimentation, and analytical models to understand the thermal phenomena of embedded electronic design and to explore the thermal design space. Numerical models ascertain the effect of heat spreaders and polymer composite substrates on the thermal performance, while physical experimentation of an embedded electronic artifact ensures the accuracy of the numerical simulations and the practicality of the thermal design. Analytical models using thermal resistance networks predict the heat flow paths within the embedded electronic artifact as well as the role of conductive fillers used in polymer composites. [S1043-7398(00)00102-X]

This paper introduces an algorithm that focuses on the placement of the power dissipating chips for multichip module applications. The main design issue is addressed on the chip placement to achieve uniform thermal distribution. Our approach to the placement problem is based on the modified force-directed placement method. The proposed thermal force-directed placement method is to relate the force equations to the power dissipation values of the individual bare chip. Examples of multichip placement are presented. The finite element simulation results are also investigated and compared with quadrisection placement methods. [S1043-7398(00)01002-1]