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In this paper, we propose an I-shaped SiGe fin tunnel field-effect transistor (TFET) and use technology computer aided design (TCAD) simulations to verify the validity. Compared to conventional Fin TFET on the same footprint, a 27% increase in the effective channel width can be obtained with the proposed TFET. The proposed Fin TFET was confirmed to have 300% boosted on-current (I on), 25% reduced subthreshold swing (SS), and 52% lower off-current (I off) than conventional Fin TFET through TCAD simulation results. These performance improvements are attributed to increased effective channel width and enhanced gate controllability of the I-shaped fin structure. Furthermore, the fabrication process of forming an I-shaped SiGe fin is also presented using the SiGe wet etch. By optimizing the Ge condensation process, an I-shaped SiGe fin with a Ge ratio greater than 50% can be obtained.

In this paper, it is shown that MOL capacitance reduction is one of the major performance boosting knobs for the tunneling field effect transistor (TFET) used for logic application. Low driving current is the weakness of TFET in terms of switching speed, however it can gain advantage fully from reducing MOL capacitance owing to negligible impact of MOL resistance degradation. We have proposed partial contact etching and gate height lowering to reduce MOL capacitance. As a result, 7.3% of delay improvement and 9.0% of reduced energy consumption is achieved with optimized MOL structure.

In this paper, we propose a new type of nonvolatile memory (NVM) device based on a tunnel field-effect transistor (TFETs) with Ferroelectric HfO₂ sidewall. By simply utilizing the ferroelectricity of orthorhombic HfO₂ and conventional sidewall spacer technique, TFET can operate as a NVM device. The polarized charges in the ferroelectric HfO₂ spacer induced by program/erase pulse modulate the tunneling barrier between the source and channel; thus, change the threshold voltage (Vt) of TFET. The proposed NVM TFET has lower subthreshold swing (SS) and higher on/off ratio than conventional NVM TFETs while maintaining equivalent program/erase efficiency. Further-more, we also investigate the optimal HfO₂ sidewall formation conditions to achieve higher NVM performances.

In this paper, we propose an I-shaped SiGe fin tunnel field-effect transistor (TFET) and use technology computer aided design (TCAD) simulations to verify the validity. Compared to conventional Fin TFET on the same footprint, a 27% increase in the effective channel width can be obtained with the proposed TFET. The proposed Fin TFET was confirmed to have 300% boosted on-current (

In this paper, we propose a new type of nonvolatile memory (NVM) device based on a tunnel field-effect transistor (TFETs) with Ferroelectric HfO₂ sidewall. By simply utilizing the ferroelectricity of orthorhombic HfO₂ and conventional sidewall spacer technique, TFET can operate as a NVM device. The polarized charges in the ferroelectric HfO₂ spacer induced by program/erase pulse modulate the tunneling barrier between the source and channel; thus, change the threshold voltage (

Ferroelectric tunnel field effect transistor (Fe-TFET) having improved DC performance in comparison to the conventional TFET (c-TFET) is proposed and investigated through the technology computer-aided design (TCAD) simulation. By inserting ferroelectric material into the gate insulator of TFET, enhanced on-current (Ion) is obtained. It is attributed to the polarization characteristic of the ferroelectric materials which brings the capacitance boosting effect. Through the TCAD simulation, the characteristics of the ferroelectric material for the optimal performance conditions are also studied.

In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (8 ns) and a large on-off current ratio (107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.

In this study, we investigate a one-transistor (1T) dynamic random access memory (DRAM) cell based on a gated-thyristor device utilizing voltage-driven bistability to enable high-speed operations. The structural feature of the surrounding gate using a sidewall provides high scalability with regard to constructing an array architecture of the proposed devices. In addition, the operation mechanism, I-V characteristics, DRAM operations, and bias dependence are analyzed using a commercial device simulator. Unlike conventional 1T DRAM cells utilizing the floating body effect, excess carriers which are required to be stored to make two different states are not generated but injected from the n+ cathode region, giving the device high-speed operation capabilities. The findings here indicate that the proposed DRAM cell offers distinct advantages in terms of scalability and high-speed operations.