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This paper accelerates the critically important least-squares Monte Carlo method (LSM) in financial derivatives pricing with parallel computing. We parallelize LSM with space decomposition, turning it into an embarrassingly parallel algorithm. The program is implemented with Parallel Virtual Machine and ALGLIB. Our method gives accurate option prices with excellent speedup. Although this paper focuses on the pricing of options, the methodology is applicable to much more complex financial derivatives. [ABSTRACT FROM AUTHOR]

The many-core SoC is a future trend technology, and the process yield will face many unpredictable challenges. Nonuniform cache architecture (NUCA) can improve the performance of many-core SoC for embedded systems. It embeds a NoC into the cache memory to enhance the data access by distributing traffic loads to several banks in parallel. Providing fault-tolerant mechanism in NUCA is very important because the chip can still work efficiently when some memory banks are unusable. In this paper, we design a specific router working with static and dynamic cache remapping policies to support faulty banks in NUCA. When a L2 cache bank in NUCA is unusable, static remapping policy (SRP) selects a suitable neighbor cache bank according to the collected remapping cost to assist with the cache access by considering cache status and traffic status of the router. We also propose a dynamic remapping policy (DRP) to select the suitable cache bank dynamically at runtime to fit the real loading status of neighbor nodes around the faulty bank. The experimental results show that the average improvement of the SRP is approximated to 26 %, and the average improvement of the DRP is approximated to 28 %. [ABSTRACT FROM AUTHOR]

In embedded systems, cache is commonly used to improve system performance. However, the cache consumes a large amount of power, and among the components of the cache memory, tag comparisons consume the most amount of power. Therefore, how to design a cache that does not consume so much power when comparing tags and that has a high hit ratio is an important challenge. In this paper, we propose a Tagless Instruction Cache, called TL-IC, that does not perform tag comparisons in order to save power in embedded systems. To guarantee that an instruction fetched from TL-IC is the desired instruction, instead of cache lines being used, the basic blocks of programs are placed into TL-IC. In addition, to utilize TL-IC as much as possible in order to save the most amount of power and to take into account the general-purpose and special-purpose applications, both the static allocation and the dynamic allocation of basic blocks are used to select the frequently executed basic blocks of programs in TL-IC. With a high utilization of TL-IC that does not perform tag comparisons, the power consumed in fetching instructions can be efficiently reduced. In the simulation results, we show and compare the power consumption of our proposed TL-IC, L0 cache, Linebuffer, and TH-IC. [ABSTRACT FROM AUTHOR]

In this paper, we propose a high performance routing protocol and a long lifetime routing protocol by considering the fact that the bandwidth between two mobile nodes should be different when distances are different. In the high performance routing protocol, to reduce the number of rerouting times, we take the bandwidth issue into account to choose the path with the capability to transmit the maximum amount of data with the help of the GPS. With exchanging the moving vectors and the coordinates of two adjacent mobile nodes, the possible link lifetime of two adjacent mobile nodes can be predicted. Subsequently, a path with the maximal amount of data transmission can be found. With regard to our proposed long lifetime routing protocol, to maximize the overall network lifetime, we find a path with the maximal remaining power after data transmission. With the link bandwidth and the desired amount of data transmitted, the consumption power is computed to obtain the remaining power of a mobile node. Accordingly, we can choose the path with the maximal predicted remaining power to maximize the overall network lifetime. In the simulation, we compare our high performance routing protocol with the AODV and LAWS in terms of throughput, rerouting (path breakage), and route lifetime. With respect to power consumption, we compare our proposed power-aware routing protocol with the POAD and PAMP in terms of the overall network lifetime and the ration of survival nodes to the all nodes. [ABSTRACT FROM AUTHOR]

In fault-tolerant multistage interconnection design, the method of providing disjoint paths can tolerate faults, but it is complicated and hard to choose a collision-free path in disjoint paths networks. A network with disjoint paths can concurrently send more identical packets from the source node to increase the arrival ratio or backtrack a packet to the source and take the other disjoint path, but these two methods might increase the collision ratio. In contrast, a dynamic rerouting method finds an alternative path that tolerates faults or prevents collisions. In this paper, we present methods of designing dynamic rerouting networks. This paper presents (1) three design schemes of dynamic rerouting networks to tolerate faults and prevent collisions; (2) design schemes that enable a dynamic rerouting network to use destination tag routing to save hardware cost in switches for computing rerouting tags; (3) a method to prevent a packet from re-encountering the faulty element again after rerouting to reduce the number of rerouting hops and improve the arrival ratio; and (4) simulation results of related dynamic rerouting networks to realize the factors which influence the arrival ratio including the fault tolerant capability and the number of rerouting hops. According to our proposed design schemes and according to our analysis and simulation results, a designer can choose an applicable dynamic rerouting network by using cost-efficient considerations. [ABSTRACT FROM AUTHOR]

In fault-tolerant interconnection designs, many prior researches suggest good use of disjoint paths to improve the reliability of interconnection networks. Although disjoint paths increase reliability, they always cost the throughput penalty. To address the problems of both performance and fault-tolerant capability, the following issues should be carefully considered: (1) guarantee of at least two disjoint paths, (2) easy rerouting between disjoint paths, (3) keep low rerouting hops, (4) solve the occurrences of packets’ collision. In this paper, we consider these issues to design a fault-tolerant network called CSMIN (Combining Switches Multistage Interconnection Network). CSMIN provides two disjoint paths to guarantee one fault-tolerant and can dynamically reroute packets between these two paths to solve the collision situation. In other words, to switch packets between these two disjoint paths easily, CSMIN causes these two disjoint paths to have regular distances at each stage. Accordingly, a packet can be dynamically sent to the other disjoint path if it encounters a faulty or busy element. In addition, CSMIN presents low rerouting hops (an average of one rerouting hop) to maintain a low collision ratio. From the simulation result, CSMIN performs with a better arrival ratio than Gamma and other related disjoint paths networks do. [ABSTRACT FROM AUTHOR]