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The implementation of turn restrictions represents a critical research challenge in chiplet-based systems, with the objective of achieving deadlock-free communication. Nevertheless, existing methodologies encounter difficulties in terms of computational complexity, which impedes the design process. Moreover, as the scale of the problem increases, the cost of addressing it becomes increasingly untenable. In this paper, we introduce the efficient turn restrictions setting (ETRS) method to reduce the computational cost of implementing turn restrictions for boundary routers in chiplet-based systems. In stage 1, we present a symmetry-based preprocessing algorithm (SBPA). SBPA exploits the symmetry inherent in chiplet topologies by generating multiple sets of identical modes, ensuring that scenarios with the same objective function value are calculated only once per iteration. In stage 2, a heuristic selection algorithm (HSA) for turn restrictions based on NSGA-II is proposed as a means of searching for approximately optimal solutions and of solving the problem quickly. In stage 3, different filtering criteria are introduced to evaluate the Pareto fronts of HSA for making decisions on the placement of boundary routers and their turn restrictions. Evaluation results reveal that the proposed ETRS method surpasses existing solutions in terms of computation efficiency. Moreover, it delivers satisfactory optimal objective values. [ABSTRACT FROM AUTHOR]