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Considering the trend of scaling down conventional technologies toward next-generation devices and the importance of new practical and efficient procedures in increasing the efficiency of digital computing circuits, this paper presents three full adder circuits. Suggested circuits, named Design-1 to Design-3, are proposed based on FinFET technology with channel length of 11 nm. In order to optimize energy consumption and area occupation, they have been implemented based on approximate computing with 4, 10, and 12 transistors, respectively. The main characteristics of the presented circuits lie in their utilization of the gate diffusion input technique, which has resulted in the generation of only three errors in their output. Diverse objectives for error generation have been incorporated into these circuits, positioning them as highly accurate competitors when compared to the most state-of-the-art designs. Also, due to the use of low number of transistors, which has led to low internal nodes, these circuits are in a favorable position in terms of power consumption and speed. To evaluate these circuits, extensive simulations are conducted considering various implementations, including single-bit configurations and integration within 4-bit ripple carry adders with 2 and 4 approximate bits. Based on the figure of merits used consist of diverse design parameters, Design-1 with the least number of transistors has a difference of about 85% improvement compared to the nearest competitor, while design-2 and design-3 circuits are also placed in desirable rankings. [ABSTRACT FROM AUTHOR]