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To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.sysarc.2006.10.010 Byline: Woo-Chan Park (a), Cheong-Ghil Kim (b), Duk-Ki Yoon (a), Kil-Whan Lee (b), Il-San Kim (b), Tack-Don Han (b) Keywords: Computer graphics; Graphics processors; Processor architectures; Memory structures; Parallel processors Abstract: Current rendering processors are aiming to process triangles as fast as possible and they have the tendency of equipping with multiple rasterizers to be capable of handling a number of triangles in parallel for increasing polygon rendering performance. However, those parallel architectures may have the consistency problem when more than one rasterizer try to access the data at the same address. This paper proposes a consistency-free memory architecture for sort-last parallel rendering processors, in which a consistency-free pixel cache architecture is devised and effectively associated with three different memory systems consisting of a single frame buffer, a memory interface unit, and consistency-test units. Furthermore, the proposed architecture can reduce the latency caused by pixel cache misses because the rasterizer does not wait until cache miss handling is completed when the pixel cache miss occurs. The experimental results show that the proposed architecture can achieve almost linear speedup upto four rasterizers with a single frame buffer. Author Affiliation: (a) Department of Computer Engineering, Sejong University, 98 Kunja-Dong, Kwangjin-Ku, Seoul 143-747, Republic of Korea (b) Department of Computer Science, Yonsei University, 134 Shinchon-Dong, Seodaemun-Ku, Seoul 120-749, Republic of Korea