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A direct growth approach using composite metamorphic buffers was employed for monolithic integration of InP-based high electron mobility transistors (HEMTs) and heterojunction bipolar transistors (HBTs) on Ge and Ge-on-insulator (GeOI)/Si substrates using molecular beam epitaxy. GaAs layers nucleated on these substrates and grown to a thickness of 0.5μm were optimized to minimize the nucleation and propagation of antiphase boundaries and threading dislocations, and exhibited an atomic force microscopy rms roughness of ∼9A and x-ray full width at half maximum of ∼36arcsec. A 1.1μm thick graded InAlAs buffer was used to transition from the GaAs to InP lattice parameters. The density of threading dislocations at the upper interface of this InAlAs buffer was ∼107cm−2 based on cross-sectional transmission electron microscopy analyses. HEMT structures grown metamorphically on GeOI/Si substrates using these buffer layers demonstrated transport properties equivalent to base line structures grown on InP substrates...

High gain AlGaAs∕GaAs heterojunction bipolar transistors grown on SiGe∕Si substrate have been fabricated. Measured peak dc current gain of ∼100 is obtained for a device with emitter area of ∼1.6×103μm2, with base concentration of 1×1019cm−3. The dominant base current component is discussed and determined. The breakdown characteristic is studied and compared with that of the device grown on GaAs substrate. Our experimental results demonstrate that SiGe∕Si substrate could provide a robust method for monolithic integration of high speed GaAs-based electronic devices with silicon-based circuitry.

In this article, we demonstrate the influence of substrate temperature during migration-enhanced epitaxy (MEE) process of GaAs epitaxy on a vicinal surface of Ge (100), 6° offcut towards the (111) plane. It was found that the offcut surface is not the sufficient condition for suppressing the formation of antiphase domains at the GaAs∕Ge interface. Rather, it has to be complemented by low substrate temperature during the MEE process. GaAs grown at 250°C, the lowest temperature among all the samples, exhibits the smoothest surface and best structural and optical qualities, as characterized by atomic force microscopy, cross-sectional transmission electron microscopy, and low-temperature photoluminescence, respectively. At this substrate temperature, As dimers are adsorbed onto the substrate surface more readily with negligible reevaporation, ensuring complete coverage on the Ge surface with double-atomic steps. Complete coverage by As proved to be crucial in preventing the occurrence of inversion boundaries,...

Monolithic integration of different electronic circuit elements onto a single chip is beneficial for the purpose of reducing overall system cost as well as improving performance and reliability. Integrating a power unit onto a silicon chip requires the implementation of a thin-film solid-state battery that is compatible with existing silicon integrated circuit technology in terms of manufacturing methods, materials, and performance. One of the materials in the battery industry, studied by us, is silicon dioxide (SiO2). The high level of process control for thin SiO2 layers which is a result of microelectronic advances, its insulating properties, and its past reported permeability to light ions have motivated us to exploit SiO2 as a solid-state electrolyte in our integrated thin-film battery. This SiO2 electrolyte layer is thermally grown from an amorphous silicon (a-Si) thin layer deposited on doped polycrystalline silicon (polysilicon) which serves as the anode against a thin-film-sputtered LiCoO2 cathod...

The authors report the sudden rise in threading dislocation density in Ge-rich relaxed graded SiGe layers grown at higher growth temperatures (T>550°C). They attribute this rise in threading dislocation density in relaxed Ge to dislocation nucleation. This observation is contrary to conventional graded buffers in Si-rich material, where higher growth temperatures result in reduced threading dislocation densities (TDDs). Additionally, a coupling effect between the effective strain during graded buffer growth and the growth rate was observed, as evidenced by increased TDD values at reduced growth rates. They conclude that reduced growth rates allow more time for the surface to evolve (i.e., roughen) during growth, thereby trapping mobile dislocations and necessitating the nucleation of additional dislocations to continue relaxing the structure.

Strain-relaxed, compositionally graded InGaP layers grown by atmospheric-pressure metalorganic vapor phase epitaxy (APMOVPE) have previously been found to exhibit unusual contrast in transmission electron microscopy (TEM). The features that generate this contrast were termed “branch defects.” Branch defects have been shown to pin threading dislocations and are thus undesirable features for the realization of low dislocation density semiconductors. In this study, we compare the properties of branch defects formed during optimized, relaxed, graded InGaP buffer deposition in two different reactor configurations: a commercial, multiwafer, low-pressure reactor and a custom-built, atmospheric-pressure research reactor. Branch defect formation is further characterized via the introduction of in situ annealing interruptions during graded buffer deposition in the atmospheric-pressure system. Branch defects are observed in material from both reactor systems, suggesting that they are a phenomenon intrinsic to InGaP ...

The stability and composition of the Ni–germanosilicided films formed on relaxed Si1−xGex alloy has been studied in the temperature range of 400–900 °C. During the solid phase thermal reaction between Ni and Si1−xGex, a nickel–germanosilicide Niy(Si1−wGew)1−y ternary phase (w⩽x and y≈0.5) and a Ge-rich Si1−zGez phase (z>x) have been found. In the lower annealing temperature range of 500 °C, the Ge composition in the nickel–germanosilicide phase is similar to that of the Si0.75Ge0.25 substrate. At the same time, germination of Si1−zGez (z>x) takes place within the germanosilicide film. At higher annealing temperatures, Ni thermodynamically prefers to react with Si compared to Ge, and as a result, Ge segregates out from the germanosilicide grains to enrich Ge in the formed Si1−zGez (z>x) grains in between the germanosilicide grains. On the other hand, the size of the germanosilicide grains increases almost linearly with annealing temperature while that for the Si1−zGez grains remains almost constant up to a...

Numerous applications require the growth of planar strained-layer heterostructures on relaxed Si1−xGex. After briefly reviewing these applications as well as the challenges in growing such heterostructures, we provide experimental examples illustrating the influence of lattice mismatch, growth temperature, and film composition on the morphology of thin strained layers in the Ge–Si alloy system. Procedures for growing strained Si and strained Ge single and double heterostructures via ultrahigh vacuum chemical vapor deposition are described in detail. We demonstrate planar growth of strained Ge layers with lattice mismatches as high as 2%, planar Si layers on any Si1−xGex lattice constant, and double heterostructures that are comprised of a strained Ge layer capped with strained Si. Notably, the techniques described here have already been applied to the fabrication of extremely high mobility p- and n-channel metal–oxide–semiconductor field-effect transistors and germanium-on-insulator substrates.

Improved GaAs/AlGaAs quantum well lasers were fabricated with longer lifetimes, higher efficiencies, and lower threshold current densities than previously reported devices on Ge/GeSi relaxed graded buffers on Si substrates. Uncoated broad-area lasers operated continuously at 858 nm with a differential quantum efficiency of 0.40 and a threshold current density of 269 A/cm2. Similar devices fabricated on GaAs substrates demonstrated nearly identical performance. Operating lifetimes on Si substrates were nearly 4 h, a 1 order of magnitude improvement over previous devices. In addition, strained InGaAs quantum well lasers have been operated continuously at room temperature on Ge/GeSi/Si substrates with a differential quantum efficiency of 0.26 and a threshold current density of 700 A/cm2. Electroluminescence analyses of the failure behavior of both types of devices have suggested that recombination-enhanced defect reactions are limiting laser lifetime on Si substrates.

Relaxed SiGe-on-insulator (SGOI) was fabricated using a bond/etch-back process. Ultrahigh-vacuum chemical vapor deposition was used to grow a SiGe graded buffer on a Si substrate, creating a relaxed Si0.75Ge0.25 virtual substrate. The SiGe graded buffer surface was then polished, and a second ultrahigh-vacuum chemical vapor deposition growth was performed to deposit a strained Si etch stop layer followed by a Si0.75Ge0.25 layer. The wafers were bonded to oxidized Si handle wafers, and the wafer pairs were annealed. The backsides of the SiGe virtual substrates were ground and etched in KOH. Since the KOH etch stops at the 20% Ge region in the graded layer, the remaining SiGe was then removed using a HF:H2O2:CH3COOH (1:2:3) solution. The resulting SGOI structure was characterized using transmission electron microscopy and atomic force microscopy; in addition, etch-pit density measurements revealed a threading dislocation density of about 105 cm−2.

Surface channel strained Si metal–oxide–semiconductor field-effect transistors (MOSFETs) are a leading contender for future high performance complementary metal–oxide–semiconductor (CMOS) applications. The carrier mobility enhancement of these devices is studied as a function of channel strain, and the saturation behavior for n- and p-channel devices is compared. Carrier mobility enhancements of up to 1.8 and 1.6 are achieved for n- and p-channel devices, respectively. The process stability of strained Si MOSFETs is also studied, and carrier mobility enhancement is shown to be robust after well implantation and virtual substrate planarization steps. The effects of high-temperature implant activation anneals are also studied. While no misfit dislocation introduction or strain relaxation is observed in these devices, increased interface state densities or alloy scattering due to Ge interdiffusion are shown to decrease mobility enhancements. Channel thickness effects are also examined for strained Si n-MOSFE...

This study explores the dislocation dynamics of strain relaxation in graded composition buffers of InxGa1−xP grown on GaP (InxGa1−xP/GaP) by metalorganic vapor phase epitaxy. Transmission electron microscopy, cathodoluminescence imaging, atomic force microscopy, and triple-axis x-ray diffraction are applied to the characterization of InxGa1−xP/GaP with final compositions ranging from x=0.09 to x=0.39 and growth temperatures ranging from 650 to 810 °C. The previously reported escalation of defect density with continued grading of InxGa1−xP/GaP beyond x∼0.3 is discovered to be due to the formation of dislocation pileups. A new defect microstructure with a branching morphology and featuring sharp local strain fields, hereafter referred to as branch defects, is observed to pin dislocations and cause the dislocation pileups. Branch defect morphology varies strongly with growth temperature, becoming significantly stronger with increasing growth temperature and causing severe material degradation above 700 °C. F...

The epitaxial growth of GaAs on Si substrates through the use of a Ge/graded Si1−xGex/Si buffer layer would allow monolithic integration of GaAs-based opto-electronics with Si microelectronics. As an initial step toward this goal, this study examines factors which influence the quality of GaAs growth by molecular beam epitaxy (MBE) on bulk Ge substrates. Key findings include the need for an epitaxial Ge smoothing cap deposited in the MBE chamber, the significant detrimental effect of As overpressure on the resultant GaAs crystalline quality, and the efficiency of a very thin (∼3 nm) migration enhanced epitaxy (MEE) nucleation layer at suppressing both anti-phase domain (APD) formation and interdiffusion across the GaAs/Ge heterointerface. Using this developed optimized growth process, APD-free GaAs on Ge is obtained which has undetectable Ga and Ge cross-diffusion, and As diffusion into the substrate at ⩽1×1018 cm−3. Preliminary results for growths on Ge/Si1−xGex/Si substrates are also presented.