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Si3N4 ceramic as a tool material shows promising application prospects in high-speed machining fields; however, the required high mechanical properties and low-cost preparation of Si3N4 ceramic tool materials restrict its application. Herein, synergistic reinforced Si3N4 ceramic tool materials were fabricated by adding β-Si3N4 seeds, inexpensive Si3N4 whiskers and TiC particles into coarse commercial Si3N4 powder (D50 = 1.5 μm), then sintering by hot-pressing with low temperature and short holding time (1600 °C—30 min—40 MPa). The phase assemblage, microstructure evolution and toughening mechanisms were investigated. The results reveal that the sintered Si3N4 ceramics with synergistic reinforcement, compared to those with individual reinforcement, present an enhancement in relative density (from 94.92% to 97.15%), flexural strength (from 467.56 ± 36.48 to 809.10 ± 45.59 MPa), and fracture toughness (from 8.38 ± 0.19 to 10.67 ± 0.16 MPa·m1/2), as well as a fine Vickers hardness of 16.86 ± 0.19 GPa. Additionally, the various reinforcement modes of Si3N4 ceramics including intergranular fracture, crack deflection, crack bridging and whiskers extraction were observed in crack propagation, arising from the contributions of the added β-Si3N4 seeds, Si3N4 whiskers and TiC particles. This work is expected to serve as a reference for the production of ceramic cutting tools. [ABSTRACT FROM AUTHOR]

CMOS integrated circuits are vulnerable to electrostatic discharge (ESD); therefore, ESD protection circuits are needed. On-chip ESD protection is important for both component-level and system-level ESD protection. In this work, on-chip ESD protection circuits for multi-Gbps high-speed applications are studied. π-shaped ESD protection circuit structures realized by staked diodes with an embedded silicon-controlled rectifier (SCR) and resistor-triggered SCR are proposed. These test circuits are fabricated in CMOS technology, and the proposed designs have been proven to have better ESD robustness and performance in high-speed applications. [ABSTRACT FROM AUTHOR]

This study found that biochar made from grapevines (GVC), an agricultural waste product, can be used as a nucleating agent to promote the crystallization of polylactic acid (PLA). Differential scanning calorimetry (DSC) analysis of GVC/PLA composites showed that different particle sizes (200 and 100 mesh size) and amounts (1 wt%, 10 wt%) of biochar affect the re-crystallization of PLA, with 200 mesh GVC in the amount of 10 wt% being the most significant. In addition, it was found that there were two peaks related to imperfect and perfect crystals in the Tm part for GVC/PLA composites. TGA analysis showed that adding GVC tends to lower the maximum decomposition temperature of PLA, revealing that GVC may accelerate the degradation reaction of PLA. This research also studied the effects of GVC in various particle sizes and amounts on the mechanical properties and degradation of PLA. The results revealed that the tensile and impact strengths of GVC/PLA composite could reach 79.79 MPa and 22.67 J/m, respectively, and the increments were 41.4% and 32.1%, greater than those of pristine PLA. Moreover, the molecular weight of PLA decreased as the amount of GVC increased. Therefore, GVC particles can be used as reinforcing fillers for PLA to improve its mechanical properties and adjust its molecular weight. These agricultural-waste-reinforced biocomposites can reduce both greenhouse gas (GHG) emissions and the cost of biodegradable polymers and achieve the goals of a circular economy. [ABSTRACT FROM AUTHOR]

In glass interposer architecture and its assembly process, the mechanical responses of interposer structure under thermocompression process-induced thermal loading and generated shrinkage of molding material are regarded as a major reliability issue. Thousands of metal-filled via are involved in glass interposers and are regarded as a potential risk that can lead to cracking and the failure of an entire vehicle. In this study, a finite element-based submodeling approach is demonstrated to overcome the complexity of modeling and the relevant convergence issue of interposer architecture. Convergence analysis results revealed that at least four via pitch-wide regions of a local simulation model were needed to obtain the stable results enabled by the submodeling simulation approach. The stress-generation mechanism during thermocompression, the coefficient of thermal expansion mismatch, and the curing process-induced shrinkage were separately investigated. The critical stress location was explored as the outer corner of the chip, and the maximum first principal stress during the thermocompression process generated on the chip and glass interposer were 34 and 120 MPa, respectively. [ABSTRACT FROM AUTHOR]

Electrode material for low-temperature co-fired diopside glass-ceramic used for microwave dielectrics was investigated in the present work. Diffusion of silver from the electrode to diopside glass-ceramics degrades the performance of the microwave dielectrics. Two approaches were adopted to resolve the problem of silver diffusion. Firstly, silicon-oxide (SiO2) powder was employed and secondly crystalline phases were chosen to modify the sintering behavior and inhibit silver ions diffusion. Nanoscale amorphous SiO2 powder turns to the quartz phase uniformly in dielectric material during the sintering process, and prevents the silver from diffusion. The chosen crystalline phase mixing into the glass-ceramics enhances crystallinity of the material and inhibits silver diffusion as well. The result provides a method to decrease the diffusivity of silver ions by adding the appropriate amount of SiO2 and appropriate crystalline ceramics in diopside glass-ceramic dielectric materials. Finally, we used IEEE 802.11a 5.8 GHz as target specification to manufacture LTCC antenna and the results show that a good broadband antenna was made using CaMgSi2O6 with 4 wt % silicon oxide. [ABSTRACT FROM AUTHOR]

The microbump (μ-bump) reliability of 3D integrated circuit (3D-IC) packaging must be enhanced, in consideration of the multi-chip assembly, during temperature cycling tests (TCT). This research proposes vehicle fabrications, experimental implements, and a nonlinear finite element analysis to systematically investigate the assembled packaging architecture that stacks four thin chips through the wafer level underfill (WLUF) process. The assembly of μ-bump interconnects by daisy chain design shows good quality. Results of both TCT data and the simulation indicate that μ-bumps with residual SnAg solders can reach more than 1200 fatigue life cycles. Moreover, several important design factors in the present 3D-IC package influence μ-bump reliability. Analytical results show that the μ-bump's thermo-mechanical reliability can be improved by setting proper chip thickness, along with a WLUF that has a low elastic modulus and a small coefficient of thermal expansion. [ABSTRACT FROM AUTHOR]

The suitability of stacked thin films for next-generation display technology was analyzed based on their properties and geometrical designs to evaluate the mechanical reliability of transparent conducting thin films utilized in flexural displays. In general, the high bending stress induced by various operation conditions is a major concern regarding the mechanical reliability of indium-tin-oxide (ITO) films deposited on polyethylene terephthalate (PET) substrates; mechanical reliability is commonly used to estimate the flexibility of displays. However, the pattern effect is rarely investigated to estimate the mechanical reliability of ITO/PET films. Thus, this study examined the flexible content of patterned ITO/PET films with two different line widths by conducting bending tests and sheet resistance measurements. Moreover, a stress-strain simulation enabled by finite element analysis was performed on the patterned ITO/PET to explore the stress impact of stacked film structures under various levels of flexural load. Results show that the design of the ITO/PET film can be applied in developing mechanically reliable flexible electronics. [ABSTRACT FROM AUTHOR]

Stress-induced failure is a critical concern that influences the mechanical reliability of an indium tin oxide (ITO) film deposited on a transparently flexible polyethylene terephthalate (PET) substrate. In this study, a cycling bending mechanism was proposed and used to experimentally investigate the influences of compressive and tensile stresses on the mechanical stability of an ITO film deposited on PET substrates. The sheet resistance of the ITO film, optical transmittance of the ITO-coated PET substrates, and failure scheme within the ITO film were measured to evaluate the mechanical stability of the concerned thin films. The results indicated that compressive and tensile stresses generated distinct failure schemes within an ITO film and both led to increased sheet resistance and optical transmittance. In addition, tensile stress increased the sheet resistance of an ITO film more easily than compressive stress did. However, the influences of both compressive and tensile stress on increased optical transmittance were demonstrated to be highly similar. Increasing the thickness of a PET substrate resulted in increased sheet resistance and optical transmittance regardless of the presence of compressive or tensile stress. Moreover, J-Integral, a method based on strain energy, was used to estimate the interfacial adhesion strength of the ITO-PET film through the simulation approach enabled by a finite element analysis. [ABSTRACT FROM AUTHOR]

A three-dimensional integrated circuit (3D-IC) structure with a significant scale mismatch causes difficulty in analytic model construction. This paper proposes a simulation technique to introduce an equivalent material composed of microbumps and their surrounding wafer level underfill (WLUF). The mechanical properties of this equivalent material, including Young's modulus (E), Poisson's ratio, shear modulus, and coefficient of thermal expansion (CTE), are directly obtained by applying either a tensile load or a constant displacement, and by increasing the temperature during simulations, respectively. Analytic results indicate that at least eight microbumps at the outermost region of the chip stacking structure need to be considered as an accurate stress/strain contour in the concerned region. In addition, a factorial experimental design with analysis of variance is proposed to optimize chip stacking structure reliability with four factors: chip thickness, substrate thickness, CTE, and E-value. Analytic results show that the most significant factor is CTE of WLUF. This factor affects microbump reliability and structural warpage under a temperature cycling load and high-temperature bonding process. WLUF with low CTE and high E-value are recommended to enhance the assembly reliability of the 3D-IC architecture. [ABSTRACT FROM AUTHOR]

This research explores the behavior of Co40Fe40W10B10 when it is sputtered onto Si(100) substrates with a thickness (tf) ranging from 10 nm to 100 nm, and then altered by an annealing process at temperatures of 200 °C, 250 °C, 300 °C, and 350 °C, respectively. The crystal structure and grain size of Co40Fe40W10B10 films with different thicknesses and annealing temperatures are observed and estimated by an X-ray diffractometer pattern (XRD) and full-width at half maximum (FWHM). The XRD of annealing Co40Fe40W10B10 films at 200 °C exhibited an amorphous status due to insufficient heating drive force. Moreover, the thicknesses and annealing temperatures of body-centered cubic (BCC) CoFe (110) peaks were detected when annealing at 250 °C with thicknesses ranging from 80 nm to 100 nm, annealing at 300 °C with thicknesses ranging from 50 nm to 100 nm, and annealing at 350 °C with thicknesses ranging from 10 nm to 100 nm. The FWHM of CoFe (110) decreased and the grain size increased when the thickness and annealing temperature increased. The CoFe (110) peak revealed magnetocrystalline anisotropy, which was related to strong low-frequency alternative-current magnetic susceptibility (χac) and induced an increasing trend in saturation magnetization (Ms) as the thickness and annealing temperature increased. The contact angles of all Co40Fe40W10B10 films were less than 90°, indicating the hydrophilic nature of Co40Fe40W10B10 films. Furthermore, the surface energy of Co40Fe40W10B10 presented an increased trend as the thickness and annealing temperature increased. According to the results, the optimal conditions are a thickness of 100 nm and an annealing temperature of 350 °C, owing to high χac, large Ms, and strong adhesion; this indicates that annealing Co40Fe40W10B10 at 350 °C and with a thickness of 100 nm exhibits good thermal stability and can become a free or pinned layer in a magnetic tunneling junction (MTJ) application. [ABSTRACT FROM AUTHOR]

Stress-induced performance change in electron packaging architecture is a major concern when the keep-out zone (KOZ) and corresponding integration density of interconnect systems and transistor devices are considered. In this study, a finite element analysis (FEA)-based submodeling approach is demonstrated to analyze the stress-affected zone of through-silicon via (TSV) and its influences on a planar metal oxide semiconductor field transistor (MOSFET) device. The feasibility of the widely adopted analytical solution for TSV stress-affected zone estimation, Lamé radial stress solution, is investigated and compared with the FEA-based submodeling approach. Analytic results reveal that the Lamé stress solution overestimates the TSV-induced stress in the concerned device by over 50%, and the difference in the estimated results of device performance between Lamé stress solution and FEA simulation can reach 22%. Moreover, a silicon–germanium-based lattice mismatch stressor is designed in a silicon p-type MOSFET, and its effects are analyzed and compared with those of TSV residual stress. The S/D stressor dominates the stress status of the device channel. The demonstrated FEA-based submodeling approach is effective in analyzing the stress impact from packaging and device-level components and estimating the KOZ issue in advanced electronic packaging. [ABSTRACT FROM AUTHOR]

The generation of a flexible printed circuit board on polymer fabrics has been a challenge over the last decade. In this work, a copper pattern was obtained on a soft substrate of filter paper/polyacrylonitrile (FP/PAN) film, where the filter paper was commercially available. The pattern of Ag particles was first produced on an Ag+-doped FP/PAN composite film, followed by electroless plating of copper using the metal silver particles as seeds. The in situ reduction of silver particles and the formation of the silver agglomeration pattern were induced by laser irradiation technology on the FP/PAN/AgNO3 composite film. A variety of characterizations indicated that the resultant copper deposition was uniform, with good conductivity properties. [ABSTRACT FROM AUTHOR]