32 results on '"Dionyz Pogany"'
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2. TIM, EMMI and 3D TCAD analysis of discrete-technology SCRs.
3. Normally-off GaN-HEMTs with p-type gate: Off-state degradation, forward gate stress and ESD failure.
4. High temperature performances of normally-off p-GaN gate AlGaN/GaN HEMTs on SiC and Si substrates for power applications.
5. ESD characterization of multi-finger RF nMOSFET transistors by TLP and transient interferometric mapping technique.
6. Statistics and localisation of vertical breakdown in AlGaN/GaN HEMTs on SiC and Si substrates for power applications.
7. IV, noise and electroluminescence analysis of stress-induced percolation paths in AlGaN/GaN high electron mobility transistors.
8. HMM-TLP correlation for system-efficient ESD design.
9. Reliability investigation of the degradation of the surface passivation of InAlN/GaN HEMTs using a dual gate structure.
10. Improved thermal management of low voltage power devices with optimized bond wire positions.
11. Application of transient interferometric mapping method for ESD and latch-up analysis.
12. Single pulse energy capability and failure modes of n- and p-channel LDMOS with thick copper metallization.
13. Investigation of smart power DMOS devices under repetitive stress conditions using transient thermal mapping and numerical simulation.
14. Transient interferometric mapping of carrier plasma during external transient latch-up phenomena in latch-up test structures and I/O cells processed in CMOS technology.
15. Thermal imaging of smart power DMOS transistors in the thermally unstable regime using a compact transient interferometric mapping system.
16. IR thermography and FEM simulation analysis of on-chip temperature during thermal-cycling power-metal reliability testing using in situ heated structures.
17. Hot spot analysis during thermal shutdown of SOI BCDMOS half bridge driver for automotive applications.
18. Experimental and numerical analysis of current flow homogeneity in low voltage SOI multi-finger gg-NMOS and NPN ESD protection devices.
19. Optimization and performance of Al2O3/GaN metal-oxide-semiconductor structures.
20. Backside interferometric methods for localization of ESD-induced leakage current and metal shorts.
21. Thermal analysis of InGaN/GaN (GaN substrate) laser diodes using transient interferometric mapping.
22. Analysis of triggering behaviour of high voltage CMOS LDMOS clamps and SCRs during ESD induced latch-up.
23. Automated setup for thermal imaging and electrical degradation study of power DMOS devices.
24. Transient interferometric mapping of smart power SOI ESD protection devices under TLP and vf-TLP stress.
25. Multiple-time-instant 2D thermal mapping during a single ESD event.
26. A dual-beam Michelson interferometer for investigation of trigger dynamics in ESD protection devices under very fast TLP stress.
27. Study of internal behavior in a vertical DMOS transistor under short high current stress by an interferometric mapping method.
28. Device Simulation and Backside Laser Interferometry--Powerful Tools for ESD Protection Development.
29. Electrical field mapping in InGaP HEMTs and GaAs terahertz emitters using backside infrared OBIC technique.
30. Experimental and simulation analysis of a BCD ESD protection element under the DC and TLP stress conditions.
31. Thermal and free carrier laser interferometric mapping and failure analysis of anti-serial smart power ESD protection structures.
32. Effect of pulse risetime on trigger homogeneity in single finger grounded gate nMOSFET electrostatic discharge protection devices.
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