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The fabrication and characterization of nanoscale n- and p-type multi-wire metal-oxide semiconductor field effect transistors (MOSFETs) with a triple gate stracture on silicon-on-insulator material (SOI) is described in this paper. Experimental results are compared to simulation with special emphasis on the influence of channel width on the subthreshold behavior. Experiment and simulation show that the threshold voltage depends strongly on the wire width at dimensions below 100 nm. It is further shown that the transition from partial to full channel depletion is dependent on channel geometry. Finally, an increased on-current per chip area is demonstrated for triple-gate SOI MOSFETs compared to planar SOI devices.

For a symmetrical DG MOSFET with two different gate-metals with two work functions, ?m1 and ?m2, a threshold voltage model is derived and presented for different L1/L2 ratios. The solid lines correspond to the model results and the symbols to the simulation results. An analytical threshold voltage model in undoped short-channel DG MOSFETs with asymmetrical dual gate material is presented. The threshold voltage model is derived based on an analytical solution for the potential distribution along the channel in the subthreshold region. For verification of the model, the potential distribution along the channel length and the threshold voltage are compared with simulation results for a wide range of the device dimensions.

An analytical CAD-oriented model for short channel threshold voltage of retrograde doped MOSFETs is developed. The model is extended to evaluate the drain induced barrier lowering parameter (R) and gradient of threshold voltage. The dependence of short channel threshold voltage and R on thickness of lightly doped layer (d) has also been analyzed in detail. It is shown that a retrograde doping profile reduces short channel effects to a considerable extent. A technique is developed to optimize the device parameters for minimizing short channel effects. The results so obtained are in close proximity with published data.

Threshold voltage analysis of surrounded gate SOI MOSFET is developed in terms of double gate and cylindrical gate MOSFETs. The temperature dependence of the threshold voltage is then studied using a Gaussian profile in the temperature range 77 to 520 K and the advantages of the surrounding gate over cylindrical and double gate SOI MOSFETs are discussed. The reduced short channel effect and operation over a large temperature range makes the surrounded gate SOI MOSFET a better choice for future VLSI/ULSI application.

Lateral Asymmetric Channel (LAC) MOSFETs with channel lengths down to 0.1 μm have been fabricated and characterized for their electrical performance. Using charge pumping, we show, for the first time, channel V T profiles obtained experimentally, demonstrating realization of asymmetric channel MOSFETs down to 0.1 μm channel lengths. Our detailed experimental characterizations show improved performance for LAC MOSFETs over conventional MOSFETs, in addition to excellent hot-carrier reliability. Based on 2-D device simulation results, we attribute the improved hot-carrier reliability in LAC MOSFETs to the reduced peak lateral electric field in the channel.

We investigate experimentally the isolation edge shape effects on the short channel characteristics, i.e. the gate length dependence, of metal oxide semiconductor field effect transistors (MOSFETs) for various isolation structures, as compared with a reference MOSFET without influence of the isolation edges. For shallow trench isolation (STI), the effect, which is enhanced for gate lengths around the onset of the short channel effect and causes the threshold voltage ( V th ) to shift to the lower voltage side than that by the short channel effect, is more prominent for the trench edge with the deeper dip. On the other hand, for the local oxidation of silicon (LOCOS) isolation with an elevated field oxide edge (i.e. the bird’s beak), the effect, which is also enhanced around the appearance point of the short channel effect, causes the V th values to go in the opposite direction to the case of STI. These results indicate that the isolation edge effect depends on the gate length and can be decribed in terms of the surface potential at the isolation edge being modulated by the mixing between the short channel and the isolation edge effect.

SiC MESFETs with a narrow channel layer are proposed to alleviate the short-channel effects, in particular the drain-induced barrier lowering (DIBL) effect that results in threshold voltage that is dependent on the gate length and the drain voltage applied. Such narrow channel layer 4H-SiC MESFETs were fabricated and characterized. The thickness and doping concentration of the channel layer are [email protected] and 8.0x10^1^7cm^-^3, respectively. The measurement results showed that the threshold voltage of the MESFETs is about -1.1V and is independent of the gate length from 1 to [email protected], and the drain voltage applied up to 40V. Good saturation behavior with fairly low output conductance was also achieved, which is desirable for small signal applications. The results obtained for the narrow channel layer MESFETs are also compared with those measured for conventional devices with thicker channel layer of [email protected] and doping concentration of 2.5x10^1^7cm^-^3.

Threshold voltage Vth instabilities observed in deep submicron n-MOSFETs after Hot Carrier Injection (HCI) are analyzed in details. A “quasi-uniform” approach for analyzing degradation effects is proposed along with a study of the “turn-over” phenomenon. Besides, the experimental Vth variation is accurately modeled.

Minority carrier mobility has been extracted from measurements on NMOS transistors with effective channel lengths down to 0.35 ?m within the temperature range 208-403 K. The results indicate a significant mobility reduction for short channel devices at temperatures below 300 K. Furthermore, a slight increase of the threshold voltage was observed in the short channel region. Both effects can be explained by an inhomogeneous lateral doping profile within the channel, which was confirmed with 2-dimensional device simulation.