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Different metallization options that allow filling 30nm 1/2pitch interconnect trenches have been explored and their full reliability performance has been benchmarked to conventional PVD TaNTa/PVD Cu seed based metallizations. CVD Co as seed enhancement layer shows no deterioration in barrier performance and improved electromigration performance, but the activation energy for electromigration was 0.68+/-0.20eV, which is at the lower end of the expected value of 0.85-0.95eV for this parameter. When integrating our trenches in a k=3.2 non-porous SiCOH low-k material, PVD RuTa barriers with 90%Ru and 10%Ta show degraded barrier performance and significant lowering of activation energy for electromigration (0.59+/-0.05eV) while when using SiO"2 as intermetal dielectric, no significant reliability deterioration is observed. Finally, it is shown that, using an optimized PVD Cu seed, standard PVD TaNTa-barriers give excellent barrier performance and that typical electromigration lifetime specs can be met with this metallization scheme down to 30nm 1/2pitch.

As an alternative to W contacts currently used in MOSFETs for DRAM, Cu contacts using self-aligned Ta-silicide and Ta-based barrier were studied experimentally. The silicidation of PVD Ta layers was studied first on 300mm blanket Si wafers. The developed method was applied to patterned wafers in the contacts, that land on poly gate and active areas of NMOS, with a sequence including the PVD of Ta, a silicidation annealing, a Ta-based Cu diffusion barrier and a Cu seed for plating the Cu plug. X-ray diffraction (XRD), X-ray reflection (XRR) and sheet resistance tests of the blanket wafers show that a Ta layer of about 10nm reacts with Si substrate and forms TaSi"2 at 650^oC in a reducing ambient. Cross-sectional SEM observation reveals that the selected processing flow fills the 90nm contacts. Top-view SEM observation on the samples after 420^oC sintering demonstrates that the Cu diffusion barrier is effective. I"o"n-I"o"f"f curves of the devices show a performance for NMOS comparable to the reference samples which use Ni(Pt)Si and the same barrier and Cu contacts, indicating that the stack of the barrier/TaSi"2/p-type Si has a contact resistance comparable to the barrier/Ni(Pt)Si/p-type Si.

PVD Ta-based and ALD TaN layers were studied as Cu diffusion barriers on poly-silicon, NiSi and CoSi"2 for Cu contact applications. The effectiveness of nanometer-thick layers, deposited in manufacturing compatible chambers on 200 and 300mm wafers, is evaluated by detection of Cu-silicidation temperature using high temperature in situ XRD. It is found that Si diffuses into the @a-Ta lattice for PVD barriers between 300 and 500^oC, and induces Ta silicidation at 600^oC. The agglomeration of TaSi"2 seems to be responsible for the damage of barrier continuity and cause subsequent Cu-silicidation. The growth of ALD TaN on different surfaces of NiSi was studied by XRF, RBS and XRR. The growth curves show excellent linearity as a function of thickness. TOF-SIMS shows closed layers after 60 ALD cycles. In situ XRD reveals that the failure temperature of 4nm thick ALD layers is higher than 500^oC. It is found that the failure of 3 and 4nm ALD TaN layers in Cu/barrier/NiSi stacks is a diffusion controlled process, with an activation energy Q of ~2.2eV and a pre-exponential factor D"0 of ~3.8x10^-^3cm^2/s.

For the PMD in a next generation memory device, two kinds of newly developed ultra low-k MSQ materials (k 500^oC. The thermal stability of the low-k MSQ is correlated with the amount of Si-X (X=H or CH"3), the ratio of Si-X to Si-O, and the structure of the Si-O bonds. With PE-SiO"2 and PE-SiN capping on HSQ, the k-value of

In this paper, we report on the integration of a spin-on low-k material (ENSEMBLE(TM) PMD) at the pre-metal dielectric (PMD) level of CMOS logic circuits processed using 0.13@mm node modules. Modifications to the conventional integration flow, where high-density plasma phospho-silicate glass (HDP-PSG) is used as PMD material, are made to the planarization steps and etch/strip sequence. Although on stand-alone transistors there is no measurable impact of the lower capacitance, a significant decrease of the switching delay of invertors in ring oscillator structures loaded with a metal/poly plate capacitor is observed. This demonstrates the possible positive impact of low-k on the performance of circuits of which the lowest level of back-end routing has a large overlap to underlying silicided areas.

Time Dependent Dielectric Breakdown performance of a fully dense and a porous metal diffusion barrier was evaluated on a porous methyl-silsesquioxane low-k material. By changing the barrier deposition process, the barrier integrity on damascene sidewalls can be improved and sealing of the low-k sidewalls is achieved with a barrier thickness value of about 8 nm. A clear correlation between barrier integrity and interconnect reliability was evidenced and an improved barrier integrity leads to increased lifetimes.