Search

Transparent ferroelectric field-effect transistors of oxidic thin films have been fabricated, showing a memory effect with an on/off ratio of the channel conductance of more than three orders of magnitude. The devices consist of a 10 nm n -type SnO 2 :Sb semiconductor channel with a 10 nm BaZrO 3 capping layer, In 2 O 3 :Sn contact pads, a 250 nm PbZr 0.2 Ti 0.8 O 3 layer as a ferroelectric insulator, and conducting SrRuO 3 as gate electrode. After deposition, the layers were structured by means of reactive ion etching. All materials were structured with a lithographically defined mask in a CHF 3 Ar plasma. Etching with CHF 3 Ar does not produce any volatile etch products but contrary to pure Ar sputter etching, no redeposited materials were found on the structures.

This review deals with the tasks involved in integrating ferroelectric thin films for memory applications. Main emphasis is put on process integration. Some of the results presented (especially dry etching ones) come from the European ESPRIT project called FELMAS. The compatibility of CMOS devices and ferroelectric capacitors is discussed and main issues toward the development of VLSI memories, are outlined.

Several metal oxide perovskites and Bi layered perovskites are of substantial interest for integrated circuit memories. Strontium titanate, barium strontium titanate, and lead zirconate titanate based paraelectrics are of particular interest for dynamic memory applications since they have high charge storage densities, low leakage currents, and resistance against time dependent dielectric breakdown sufficient to achieve gigabit densities and beyond. The high remanent polarization of ferroelectric lead zirconate titanate and strontium bismuth tantalate hold out the promise of low-voltage, high-speed, non-volatile memories. Advances are being made in the reliability of ferroelectric memories.

Modified scheme of the non-volatile memory cell for ferroelectric SRAM is proposed allowing an enhanced reliability and essential lowering of demands to the electrical properties of the ferroelectric capacitors (FECAPs). It is shown that the successful integration of sol-gel FECAPs into a Si-based CMOS technology is possible using the common lift-off and wet-etching photolithography. The FECAPs fatigue problem and its possible physical mechanisms are discussed.

Deposition and patterning processes to produce 9×9μm ferroelectric capacitor (FECAP) structures, and the back-end processes necessary to integrate them with silicon-on-sapphire (SOS) circuits have been developed with the aim of demonstrating a 4kbit non-volatile RAM (NVRAM) on SOS. PZT thin film deposition by a sol-gel route has been characterised and dielectric, ferroelectric and fatigue measurements taken.