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A novel output stage design for four-phase ratioless dynamic logic is proposed for a low speed asynchronous pump circuit. The main features of the proposed circuit are that the precharge capacitance is reduced significantly, leading to lower power consumption, and the circuit can operate in the synchronous mode. Although more transistors are used in the circuit, there is no increase in the chip area.

Four-phase dynamic logic has been widely used to implement VLSI circuits. A technique which allows system designers to operate a custom-designed integrated circuit in different modes is to connect an input option pin to either a logic level 1 or a logic level 0 according to the specification by connecting it to Vcc or ground respectively. This method allows the designer to configure the operation of the circuit in one of the two modes. In this paper it is shown that each pin can be used to offer four modes of operation instead of two by the use of a simple multiplexing circuit. The circuit was simulated and its operation verified using the industry-standard program SPICE. The additional area required to implement the demultiplexing circuit on the chip may be offset by the saving achieved by the use of one pin to input four variables instead of two pins. Removal of an input pin from the integrated package results in the saving of silicon area on the chip as it eliminates the contact pad area and the associated input gate protection circuitry.