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In this work a Cu pillar design that combines a stiff metal pedestal with a soft polymer as buffer layer has been integrated in a dedicated test vehicle to investigate the thermo mechanical stress induced during flip chip assembly. In-situ electrical measurements of dedicated stress sensors during a Bump Assisted BEOL Stability Indentation (BABSI) test were performed to assess the strength of the bump designs. Furthermore, the package induced stress was monitored in different regions of the test chips by measuring and comparing the ION current of the stress sensors before and after packaging. By combining in-situ electrical measurements and finite element modeling it was possible to quantify the stress level induced in the Si die after packaging. Additionally, the package out of plane deformation has been measured after flip chip to laminate and after molding. The results show that the use of a stiff pedestal is very efficient to mitigate packaging induced stress. It has also been shown that the out of plane deformation is independent of the Cu pillar design.

The influence of via density and passivation thickness on the mechanical integrity of Back-End-Of-Line (BEOL) interconnects under Chip Package Interaction (CPI) loading is evaluated using a dedicated package test chip with 4 metal layers, and advanced copper/low-k processing. The reliability assessment is done using thermal cycling reliability tests, where two dedicated resistance based CPI test structures are analyzed. The data show a correlation between via density and reliability for both passivation modules, where a higher via density reduces the number of failures. In addition, the influence of passivation thickness was determined, where a thinner passivation results in a reduced number of failures. In order to visualize the failures, the interconnect stack was exposed after mechanical removal of the package overmold and Si etching. Cracks were present at the corner of the test chip.

We report a new non-destructive method to localize interconnection failures in 3-D devices. The scanning optical microscopy (SOM) technique is based on lock-in thermal laser stimulation (LI-TLS) and uses thermal waves to non-destructively map the current path in a 3-D device. We validate the method with test structures and show how the magnitude and phase of a propagating thermal wave may provide valuable 3-dimensional information on the failure location. We apply the technique on a short failed chain structure in a four level chip stack with an intensity modulated laser as a thermal wave injector and the structure under test as a detector. We confirm our results by physical failure analysis through a selective cross sectioning process.

A computationally-efficient 3D phase-field model for simulating grain growth in through silicon vias (TSVs) is presented. The model is capable of simulating grain growth in the cylindrical shape of a TSV. The results generated from the phase-field simulations are used in a finite element model with anisotropic elastic and isotropic plastic effects to investigate the large statistical distribution of Cu pumping (i.e. the irreversible thermal expansion of TSV) experimentally seen. The model thus allows to correlate the macroscopic plastic deformation with the grain size and grain orientations.

The reliability results for barrier/liner systems in different high aspect ratio (5 × 50 μm) through silicon vias (TSV) are presented. Quite a few factors can influence the TSV barrier/liner reliability performance, including the TSV trench etch process, the oxide liner material/thickness, etc. The challenges for more advanced TSV technology nodes (e.g. 3 × 40 μm) are also discussed and possible solutions are proposed.

Chip Package Interaction (CPI) gained a lot of importance in the last years. The reason is twofold. First, advanced node IC technologies requires dielectrics in the BEOL (back-end-of-line) with a decreasing value for the dielectric constant k. These so-called (ultra) low-k materials have a reduced stiffness and reduced adhesion strength to the barrier materials, making the BEOL much more vulnerable to externally applied mechanical stress due to packaging. Secondly, advanced packaging technologies such as 3D stacked IC’s use thinned dies (down to 25 μm) which can cause much higher stresses at transistor level, resulting in electron mobility shifts of the transistors. Also the copper TSV (through-silicon-via) generates local stress which affects the device performance. This paper considers both the packaging impact on BEOL integrity and transistor mobility shifts for 3D stacked IC (integrated circuit) technologies.

The crystal orientation and grain distribution of Cu6Sn5 and Cu3Sn intermetallic compounds (IMCs) in miniaturized solid-liquid interdiffusion (SLID) interconnects for 3D stacking were investigated. Therefore Cu/Sn microbumps with a diameter of 15 μm on top die (metal height 5.4 μm/3.6 μm) and Cu microbumps with a diameter of 25 μm on bottom die (metal height 9.5 μm) were used for bonding and subsequent thermal storage. The effect of the storage time (varied from 10 min to 96 h) and storage temperature (150, 240 and 260 °C) on the grain structure formation was investigated by Electron Backscatter Diffraction (EBSD). After the initial Cu6Sn5 scallops have grown together, the corresponding Cu6Sn5 layer only consists of one or two grains, which are orientated with 〈10−11〉 and 〈2−1−12〉 directions parallel to the IMC growth direction (perpendicular to substrate or Cu layer). The Cu3Sn IMC showed small columnar grains in its early growth stage, which develop into grains with a polygonal shape due to coarsening effects. Cu3Sn grains are orientated randomly at the early growth stage and tend to be orientated mostly with 〈10−10〉 and 〈2−1−10〉 parallel to the IMC growth direction at higher temperatures and longer storage times.

When Cu ‘Through-Silicon-Vias’ (TSVs) are exposed to high temperatures as typically encountered during the back-end of line (BEOL) processing, the higher coefficient of thermal expansion (CTE) of Cu forces it to expand more than Si. This causes compressive stress in the confined Cu inside the TSV. This stress can partly be released near the top of the TSV, by out-of-plane expansion of the Cu, the so-called ‘Cu pumping’. It can severely damage the BEOL layers. In this paper the effect of a pre-CMP thermal budget (temperature and time) on Cu pumping is studied for various Cu chemistries and TSV aspect ratios. It is shown that to suppress Cu pumping a pre-CMP anneal is required that is either very long or at a temperature very close to the maximum temperature used in the BEOL processing.

This paper deals with a comparison study between SnPb and SnAgCu solder joint reliability. The comparison is based on non-linear finite element modelling. Three packages have been selected: silicon CSP, underfilled flip chip and QFN package. Also the effect of thermal cycling conditions has been investigated. Comparing the induced inelastic strains in the solder joint, the lead-free SnAgCu generally scores better thanks to the lower creep strain rate. On the other hand for the CSP and flip chip package, SnAgCu scores worse for the more extreme loading conditions when the inelastic dissipated energy density is selected as damage parameter. The main reason is that due to the lower creep strain rate, the stresses become higher for SnAgCu resulting in higher hysteresis loops with more dissipated energy per cycle. For the QFN package, SnAgCu scores much better.

Adhesion is one of the main reliability concerns in electronic packages. However, the lack of standards to characterize this property makes it difficult to interpret the results. In this work, a series of shear tests have been conducted to evaluate adhesion strength of different electronic materials. Finite element analysis (FEA) is employed here to model the shear strength of microelectronic materials and to analyze the stress distribution in the specimen and substrate in order to understand this failure mechanism. The shear tool force and displacement at failure were measured experimentally and used as boundary condition for the FEA calculations. Several combinations of soft and stiff materials for specimens and substrates respectively have been evaluated in order to estimate the effects on the shear strength. The general trend from experimental and FEM results shows that soft specimens present a high concentration of stresses in the loaded surface while in the case of rigid specimens, the stresses are distributed in the whole area of contact between specimen and substrate. A proposal for calculating the shear strength was done.

IMEC VZW, MCP, EDAS, B-3001 Louvain, Belgium. IMEC VZW, Div IMOMEC, B-3590 Diepenbeek, Belgium. XPEQT, B-3980 Tessenderlo, Belgium.Soussan, P, IMEC VZW, MCP, EDAS, Kapeldreef 75, B-3001 Louvain, Belgium.

The key to bonding to copper die is to ensure bond pad cleanliness and minimum oxidation during wire bonding process. This has been achieved by applying a organic coating layer to protect the copper bond pad from oxidation. During the wire bonding process, the organic coating layer is removed and a metal to metal weld is formed. This organic layer is a self-assembled monolayer. Both gold and copper wires have been wire-bonded successfully to the copper die even without prior plasma cleaning. The ball diameter for both wires are 60 μm on a 100 μm fine pitch bond pad. The effectiveness of the protection of the organic coating layer starts from the wafer dicing process up to the wire bonding process and is able to protect the bond pad for an extended period after the first round of wire bond process. In this study, oxidization of copper bond pad at different packaging processing stages, dicing and die attach curing, have been explored. The ball shear strength for both gold and copper ball bonds achieved are 5 and 6 g/mil2 respectively. When subjected to high temperature storage test at 150 °C, the ball bonds formed by both gold and copper wire bond on the organic coated copper bondpad are thermally stable in ball shear strength up to a period of 1440 h. The encapsulated daisy chain test vehicle with both gold and copper wires bonding have passed 1000 cycles of thermal cycling test (−65 to 150 °C). It has been demonstrated that orientation imaging microscopy technique is able to detect early levels of oxidation on the copper bond pad. This is extremely important in characterization of the bondability of the copper bond pad surface.

At frequencies beyond 1 GHz, every component of the IC package contributes to the RF performance, whether required or not. In this work, we study the effects of packaging materials namely, the substrate and the globtop/underfill material on RF performance. We have measured interconnects on two area-array CSPs, the ball grid array and the polymer stud grid array using IMEC’s MCM-D technology. The measurements on the package interconnect show that the losses in the package substrate material account for about 50% of the total losses at 1.8 GHz and this drops to less than 20% at 5.2 GHz. The losses due to impedance mismatch dominate the losses especially below 10 GHz and considerable improvement in performance cannot be obtained by using an improved/expensive substrate. The other study is about the influence of globtop/underfill materials on wirebonds (through 3D EM simulations) as well as on standard 50 Ω MCM-D transmission lines (through experiments). While a higher value of dielectric constant of the globtop/underfill material is better on wirebonds, the influence of loss tangent is felt only above values of 0.1. The influence of seven different globtop/undefill materials on 50 Ω transmission lines has been used to extract their dielectric constant and loss tangent values at 30 GHz. These results are very valuable since one can hardly find the properties of globtop/underfill materials beyond 1 GHz.

The ceramic ball grid array (CBGA) packages are typically used for high I/O count area array assemblies. As the package size is large, the distance to neutral point is also high resulting in a large thermal deformation mismatch between the CBGA package and the printed circuit board (PCB). In order to cope with this problem, a special solder joint connection is used. As CBGA assemblies are used for high pin count assemblies, a full 3D thermo-mechanical modelling of an assembly to an FR4 board is not possible anymore. Therefore, a modified micro–macro methodology is proposed where only the critical solder joint is modelled in detail, while the other connections are replaced by equivalent connections. For several CBGA configurations, simulation results are correlated to thermal cycling test results. Finally, a parameter sensitivity study shows that the PCB properties have a significant influence on the solder joint reliability.

Compared with traditional test techniques, the in-situ high resolution resistometric technique allows a sensitive monitoring of thin film metallisations submitted to ’realistic’ current stress levels and reveals the occurrence of distinct reversible and irreversible processes. A review is provided of the processes observed in metallisations submitted to three regions of current stress: no current stress, low current density stress ( j MA/cm 2 ) and ‘high’ current density stress ( j>0.5 MA/cm 2 ). Discarding the contributions of the concurrent, temperature induced, masking mechanisms results in an accurate observation of the kinetics of the early stages of electromigration, revealing fundamental features such as incubation time, subsequent linear resistance increase and current and temperature dependence.

A transient thermal characterisation technique for monitoring structural degradation in microelectronic components will be presented. This non destructive package quality evaluation technique is based on indirect transient temperature response measurements and can be used to determine both the existence and location of structural defects in packaged semiconductor devices. The effect of package thermal properties on the transient temperature response is first investigated by means of finite element analysis. Practical thermal impedance measurements on a hybrid test structure and a 48-lead TSSOP illustrate the capabilities of the transient measurement technique with respect to failure characterisation in microelectronic packages.

Electromigration is a phenomenon where atoms are driven from their lattice positions due to an electric current. In general two types of electromigration systems can be distinguished: the heterogeneous system, in which electromigration failure occurs at the interface of two distinct parts on the interconnection while in the second, homogeneous case the failure occurs within the interconnection itself. The first type of electromigration is reported in this study and off-chip gold ball bonds on aluminium metallization are used as an example. In-situ electrical measurements of the resistance change as a function of time with different temperature and current stresses are performed. A good understanding of the kinetics of the resistance change could be obtained which helps in the characterisation of the processes active during the degradation of the interconnections.