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Abstract: We propose a novel resistive switching device with a W/CeO2/Si/TiN structure by incorporating a very thin Si buffer layer in the interface, the memory performance of this device such as forming voltage, operation power, and window and endurance characteristics were found to be remarkably improved compared with the performance of the device without the Si layer. This improvement was attributed to the formation of Ce-silicate and thus proper introduction of oxygen vacancies at the interface. The gradual reset process of the W/CeO2/Si/TiN device under sweeping voltage was quantitatively analyzed by parallel conductive filaments model. Our results provide a guideline for the operation voltage control for further optimizing device performance and give new insights into the gradual reset process. [Copyright &y& Elsevier]

Abstract: N-type metal–oxide–semiconductor field-effect transistor (MOSFET) with an equivalent oxide thickness (EOT) of 0.37nm has been demonstrated with La2O3 as a gate dielectric for the first time. Despite the existence of parasitic capacitances at gate electrode and inversion layer in the channel, a sufficient drain current increment in both linear and saturation regions have been observed, while scaling the gate oxide from 0.48 to 0.37nm in EOT. Therefore, continuous scaling of EOT below 0.5nm is still effective for further improvement in device performance. [Copyright &y& Elsevier]

Abstract: The chemical bonding states and electrical characteristics of SrO capped La2O3/CeO x gate dielectric have been examined. Angle-resolved X-ray photoelectron spectroscopy measurement has revealed that Sr atoms diffuse into silicate layer to form SrLa-silicate after annealing. Owing to the incorporation of Sr atoms into silicate layer, a transistor operation with an equivalent oxide thickness (EOT) below 0.5nm has been demonstrated. A strongly degraded effective electron mobility of 78cm2/Vs at 1MV/cm has been obtained, which fit well with the general trend in small EOT range below 1nm. Although process optimization is needed to improve the performance of transistors, Sr capping technique can be useful for EOT scaling. [Copyright &y& Elsevier]

Abstract: The effect of La2O3 incorporation on the spatial trap distribution in HfO2 gate dielectrics is investigated. The incorporation of La2O3 in HfO2 dielectric has been found to improve the effective mobility in addition to reduced interface-state density. The trap distribution analysis in the HfO2 layer extracted by combining the charge pumping (CP) method and the low-frequency noise (LFN) method has revealed significant reduction in the amount of traps at HfO2/SiO2-interlayer interface and in the HfO2 layer by La2O3 incorporation. [Copyright &y& Elsevier]

Highlights: [•] We observed different temperature dependences of the leakage current in CeO2/La2O3 stack. [•] The CeO2 capping layer resulted in the barrier lowering at La2O3/Si interface. [•] Poole–Frankel conduction dominating the leakage current with a barrier height of 0.119eV. [•] The oxygen atoms from the CeO2 layer also affected the current conduction at higher voltages. [Copyright &y& Elsevier]

Abstract: A novel interpretation for conductance spectra obtained by conductance method of La2O3 gated MOS capacitors has been proposed. Two distinct peaks, one with broad spectrum ranging from 10k to 200kHz and the other near 1kHz with a single time constant spectrum, have been observed at depletion condition. The former spectrum can be assigned as the interface traps (Dit ) located at the interface between La-silicate and the Si substrate by statistical surface potential fluctuation model. On the other hand, as the latter slow trap signal shows strong influence with the thickness of La-silicate layer, it can be assigned as the trappings (Dslow ) at the interface between La2O3 and La-silicate. Finally, the Dit and Dslow trends on annealing temperature are summarized. [Copyright &y& Elsevier]