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The electrical characteristics of bulk nFinFETs after total-ionizing-dose (TID) irradiation were experimentally evaluated with respect to the process variation (PV). The inconsistent transfer characteristics, particularly the different threshold voltage shifts under an identical bias condition and irradiation dose, were investigated through technology computer aided design (TCAD) simulation, considering the shallow trench isolation (STI) footing and the asymmetrical sidewall. The influence that the bias condition had, as an important factor including ON, OFF, and transmission gate (TG), is included in this paper to better illustrate the PV dependence. The HfO 2 high-ĸ metal gate, the STI, and the PV dependent geometry were some of the influences that occurred within the degradation of electrical performances as the TID increased. A radiation-hardness strategy was proposed in order to improve the electrical properties of the FinFET devices in the radiation environments.

The layout effect influences the performance of nanoscale devices with advanced strain engineering, considering that the size of a technology node continuously shrinks to ≤ 20 nm. Transistors with a long gate width could be fabricated, and the portion that protrudes outside the channel region could be located on a soft shallow trench isolation region and even across the dummy active region of diffusion. Induced strained silicon technology should be considered when managing and enhancing mobility gain in devices with narrow channel widths. Thus, we fabricated a 20 nm silicon-based n-type metal-oxide-semiconductor field-effect transistor with a Si0.75Ge0.25 alloy channel and a + 3.0 GPa tensile contact etch stop layer as stressors. The transistor was utilized at different dummy gate arrays and dummy poly pitches. The fabricated device was subjected to oriented stress simulation, and the relationship between the piezoresistance effect and the stress component within the device channel was investigated. The best performance, which was 40% higher than that of conventional transistors, was observed in the transistor with 100 nm gate width.

The influences of silicon-rich shallow trench isolation (STI) on total ionizing dose (TID) hardening and gate oxide integrity (GOI) in a 130 nm partially depleted silicon-on-insulator (SOI) complementary metal-oxide semiconductor (CMOS) technology are investigated. Radiation-induced charges buildup in STI oxide can invert the parasitic sidewall channel of the n-channel transistor, which will increase the off-state leakage current and decrease the threshold voltage for the main transistor. Compared with the general STI process, the silicon-rich STI process can significantly suppress the increase in leakage current and negative shifts in subthreshold region induced by the total dose radiation, implying TID hardening for STI trench oxide. However, the silicon-rich STI process has a deleterious impact on GOI. It leads to the thin gate oxide thickness at trench corner and lowers the gate oxide breakdown voltage. Issues of gate oxide integrity induced by silicon-rich STI are investigated in this paper, and an optimized process to solve this problem is proposed and examined. Finally, the TID response of the optimized silicon-rich STI process is presented in comparison to the general and silicon-rich STI processes.

Total ionizing dose (TID) effects are investigated in a nanosheet gate-all-around field effect transistor using three-dimensional technology computer aided design simulation. TID is a reliability concern in terms of building up trap charges in any dielectric surrounding the transistor body. In this work, the impact of trap charges on different dielectrics including gate oxide, gate spacer and shallow trench isolation is discussed. The TID vulnerabilities for various channel characteristics are compared. Methods for suppressing the manifestation of trap charges are suggested.

We studied the radiation response of 3 different 65 CMOS planar technologies at the ultra-high doses expected to be reached in the HL-LHC, the upgraded large hadron collider of CERN. All the processes studied are sensitive to radiation and show similar degradation mechanisms and, albeit with different intensities, similar dependencies on device geometry, applied polarization and temperature. The results obtained confirmed that the performance of MOS transistors exposed to ultra-high doses is mainly affected by radiation-induced charge trapped in auxiliary oxides such as shallow trench isolation oxides and spacers. The extensive data collected has been used to develop guidelines to qualify to ultra-high doses ASICs designed in the 65 technology node.

This paper proposes a method which can separate the parasitic effect from the drain current I d vs. gate voltage V g curves of MOSFETs, then uses this method to analyze degradation of experimental pMOSFETs due to hot-electron-induced punchthrough (HEIP). An I d vs. V g curve of the parasitic MOSFET formed by a shallow trench isolation (STI) is obtained by extrapolating the line of I d vs. channel width W at each V g to W = 0 μm. The I d vs. V g curves of the parasitic MOSFET indicate that HEIP caused electron trapping at the interface between SiN and the sidewall oxide of STI, but the curves of the main MOSFET indicate that HEIP caused negative oxide charges and positive interface traps in the channel region. These charges and traps decreased the threshold voltage V th of the parasitic MOSFET but increased V th of the main MOSFET. These two opposite behaviors of V th resulted in little HEIP-induced shift of V th at W = 2.5 μm. | V d | to secure ten-year HEIP lifetime of 10% shift of V th was ≤ 2.2 V at W = 0.3 μm, ≤ 3.5 V at W = 1.0 μm, and ≤ 3.6 V at W = 10 μm; these changes indicate that degradation of parasitic MOSFET influences the HEIP lifetime of narrow pMOSFET significantly.

FinFET technology compared with planar have an increased sensitivity to single-event latch-up. TCAD simulation demonstrates that the reduction in width of MOSFET, thickness of shallow trench isolation (STI) and nMOS-to-pMOS lateral spacing will reduce the holding voltage, critical charge and increase the current gain of parasitic CMOS Silicon Controlled Rectifier (SCR). Through circuit analysis, it found that the change of parasitic vertical and horizontal resistance is mainly responsible for aforementioned phenomena. In addition, we found that the common protective measures such as guard rings spacing and epitaxial substrate become increasingly difficult. Based on the current preventive methods, we think that appropriate increasing the doping depth or the width of guard rings will improve protection from Single-Event Latch-up (SEL). Moreover, we verify the effectiveness of our methods by TCAD simulation and discuss the feasibility.

This paper presents the total ionizing dose radiation performance of 0.2 μm PDSOI NMOS devices under different bias conditions. The hump effect is observed in the transfer characteristic of the back gate device instead of the front gate device after radiation. A STI bottom corner parasitic transistor model is proposed to explain this phenomenon. It also provides a simple way to extract the effective sheet charge density along the STI sidewall. Three-dimensional simulation was applied to explain the radiation effect. It shows that charge trapped in the shallow trench isolation, particularly at the bottom region of the trench oxide where the STI and the BOX are connected, is the dominant contributor to the off-state drain-to-source leakage current. The dimension of the transistor plays an important role on influencing the device’s performance after radiation. Larger off-state leakage current and radiation induced threshold voltage shift are reported in the narrow channel device than in the wide channel one. Different TID responses due to the STI process variation are also discussed.

This paper quantifies how mechanical stress induced by the hybrid shallow trench isolation affects negative bias temperature instability (NBTI) degradation of p-type channel MOSFETs (pMOSFETs) that have a strained Si/SiGe channel. As the channel length L decreased, the NBTI degradation decreased and electrical characteristics degraded. Experimental results indicate that tensile stress σt applied to the channel region decreased the energy band-gap by increasing the intrinsic carrier concentration. NBTI degradation was not affected by application of an oxide electric field to compensate for the charge that is induced differently in the Si channel during strong inversion. The distribution of the shift ΔVth of threshold voltage before and after NBTI stress in the channel region was also examined. As L decreased, the decrease of ΔVth was greater in the gate edge region than in the center region. These results show that the observed L-dependence of NBTI degradation characteristics were caused by σt in the channel region, and affected the gate edge region dominantly. Therefore, to achieve reliable high-k pMOSFETs with the strained Si/SiGe channel as L is scaled down, methods should be developed to control mechanical stress in the gate edge region.

In this paper we propose a modified model of logical effort for designing optimized buffers in multi-fingered layout scenario in the presence of process induced mechanical stress. It is observed that mechanical stresses induced by tensile and compressive Etch Stop Liner (t-ESL and c-ESL), embedded SiGe (eSiGe) and Shallow Trench Isolation (STI) are not uniform in all the fingers sharing an active region. As a result there is an unaccounted change in the drive current with the number of fingers; thereby causing an unaccounted change in the performance of logic gates implemented using multi-fingered layouts. We explore the impact of mechanical stress induced variability in inverters with multi-fingered devices and derive relationship between the logical effort (LE) and number of fingers (NFs). We use this relationship for predicting CMOS buffer delays more accurately and thus reducing the need for post-layout resizing of their transistors.

Channel width dependence of mechanical stress effects on a nanoscale n -channel metal–oxide-semiconductor field-effect transistor using the shallow trench isolation (STI) is investigated. The results indicate that the mechanical stress induced by the STI enhances mobility, off currents, and the impact ionization significantly. 841 MPa of tensile stress is extracted using the subthreshold current method. In addition, the off-state stress is measured at 125 °C, and the narrow width device is more seriously degraded than wide width devices.

This paper is focused on the analysis and optimization of power N-type LDMOS (LDNMOS) transistors ( V BR > 120 V) with the purpose of being integrated in a new generation of Smart-Power technology based upon a 0.18 μm SOI-CMOS technology. The influence of some important design parameters such as the shallow trench isolation (STI) length ( L STI ), the N-well doping profile and the relative position of the N-well mask to the STI block are analyzed in terms of voltage capability ( V BR ), specific on-state resistance ( R on-sp ) and electrical safe-operating area (SOA) by means of Technology Computer-Aided Design (TCAD) numerical simulations. The evolution of the measured and simulated V BR as a function of the substrate (handle wafer) voltage (HWV) gives good physical insight of the optimal LDNMOS drift region design configuration. LDNMOS transistors with STI lengths partially covering the drift region length leads to better combined action of R on-sp / V BR trade-off and electrical SOA results.

The effects of total ionizing dose (TID) irradiation on the inter-device and intra-device leakage current in a 180-nm flash memory technology are investigated. The positive oxide trapped charge in the shallow trench isolation (STI) oxide is responsible for the punch-through leakage increase and punch-through voltage decrease. Nonuniform radiation-induced oxide trapped charge distribution along the STI sidewall is introduced to analyze the radiation responses of input/output (I/O) device and high voltage (HV) device. At low dose level, the inversion near the STI corner caused by the trapped charge occurs more easily due to the lower doping concentration in this region, which gives rise to the subthreshold hump effect. With total dose level increase, more charge at deep region of the STI oxide is accumulated, predominating the intra-device off-state leakage current. It has been discussed that the STI corner scheme and substrate doping profile play important roles on influencing the device’s performance after radiation.

During the qualification of a new Advanced Bipolar, CMOS, DMOS (A-BCD) technology some typical failure modes were observed in this SOI process. After a short introduction of the technology and its areas of application three different failure modes will be discussed. The failures initiated during HTOL test are localized with standard PEM/OBIRCH analysis techniques. Main focus will be on the physical defects at the origin of the fail and the different techniques to reveal them. The failures are observed within the Shallow Trench Isolation (STI) module of the High Voltage components and along the edge of the Medium Trench Isolation (MTI). The root causes and the possible corrective actions will be discussed when applicable.

The sensitivity of radiation-induced source–drain leakage to the amount of recess in the shallow-trench isolation (STI) of CMOS technologies is reported. The impact of the doping profile along the STI sidewall on the magnitude of the leakage current is quantified. The sensitivity of the radiation-induced leakage current to these parameters provides insight into how process variability is manifested as variations in the radiation response.

In this work, we investigated the hot carrier (HC) generation of power silicon-on-insulator (SOI) lateral double-diffused N-type MOSFETs (LDNMOSFET) with shallow trench isolation (STI) structure under different biasing conditions. Experimental measurements of drain and substrate currents are done. Two-dimensional (2-D) device simulation is performed to provide a better insight on the electrical behaviors of the device by looking at the electric-field (EF), electron current density (JE) and impact ionization generation rate (RII) distributions in the devices. The high RII site is found to be near the STI corner instead of near the channel or field oxide area close to the gate surface in standard small signal MOSFET.

The peaked evolution of leakage current with total ionizing dose observed in transistors in 130 nm generation technologies is studied with field oxide field effect transistors (FOXFETs) that use the shallow trench isolation as gate oxide. The overall radiation response of these structures is determined by the balance between positive charge trapped in the bulk of the oxide and negative charge in defect centers at its interface with the silicon substrate. That these are mostly interface traps and not border traps is demonstrated through dynamic transconductance and variable-frequency charge-pumping measurements. These interface traps, whose formation is only marginally sensitive to the bias polarity across the oxide, have been observed to anneal at temperatures as low as 80 °C. At moderate or low dose rate, the buildup of interface traps more than offsets the increase in field oxide leakage due to oxide-trap charge. Consequences of these observations for circuit reliability are discussed.

For PMOS (p-channel metal–oxide–semiconductor) transistors isolated by shallow trench isolation (STI) technology, reverse narrow width effect (RNWE) was observed for large gate lengths such that the magnitude of the threshold voltage becomes smaller when the channel width decreases. However, PMOS transistors with small gate lengths show up a strong anomalous narrow width effect such that the magnitude of the threshold voltage becomes larger when the channel width decreases. We attribute such an anomalous narrow width effect to an enhancement of phosphorus and arsenic transient enhanced diffusion (TED) due to Si interstitials generated by the deep boron source/drain (S/D) implant towards the gate/STI edge.

A detailed experimental investigation of low frequency noise as a function of technology-induced mechanical stress in MOSFET devices is presented. Both n- and p-MOSFETs have been studied. Strain in the channel region is obtained by the Shallow Trench Isolation (STI) technique. An increasing of 1/f noise intensity when compressive mechanical stress increases has been detected in p-channel transistor. A critical discussion of this experimental finding has been proposed in the scenario of advanced generation CMOS technologies.

The flicker or low-frequency noise behaviors of the junction field-effect transistor (JFET) with source and drain shallow trench isolation (STI) regions for planner technology are studied in detail. High noise level is found in the devices with the source and drain isolation and the normalized drain flicker noise is found to be gate bias dependent. The excess noise is identified as the surface noise generated at the oxide/Si interface in the isolation regions and a model is developed to explain the bias dependencies of the noise level and frequency index of the noise spectra. Although a larger low-frequency noise was found in the STI-JFET when compared with the conventional bulk type JFET, it is still an attractive structure for integrating into CMOS technology for low-noise analog applications. The noise level can be further minimized by keeping STI region small and using a better oxidation technique for the STI passivation.

In this paper we report a detailed characterization of anomalous gate oxide conduction on isolation edges. Previously, it was shown that gate oxide can feature severe thickness variation [Liu et al., Proceedings of VLSI Symposium, 1999, p. 75; Mat. Res. Soc. Symp. 611 (2000) C4.1.1] near the top corner of the shallow trench isolation. Here, we show that this can significantly impact the tunnel I–V characteristics of gate oxide, with implications for the device performance uniformity and reliability. Comparing experimental data with accurate tunnel current simulation we demonstrate that this anomalous conduction is due to a double effect of oxide thinning and rounding of the poly/oxide interface. Furthermore, we study the impact of many process parameters on this anomalous leakage. We show that, by optimizing several process steps, it is possible to avoid this problem. Possible physical causes of this phenomenon are also addressed.

A n ovel CMOS fabrication process with a d ual g ate o xide (NDGO, thin oxide 5.0 nm, thick oxide 7.8 nm) and a shallow trench isolation (STI) top-edge rounded by a pad oxide undercut was developed for a 256M-bit mobile dynamic random access memory (DRAM) with V D =1.8 V. We present a comprehensive study on the I – V characteristics and the long-term reliability of CMOSFET fabricated by NDGO process, and compared these characteristics with those of conventional single gate oxide transistors with a gate oxide thickness 5.0–7.5 nm. While thin oxide nMOSFET have a threshold voltage of nMOSFET ( V thn ) of between 0.70 and 0.72 V and a saturation current ( I DSAT ) of between 280 and 300 μA/μm, thick oxide nMOSFET have a V thn of between 0.85 and 0.90 V and an I DSAT of between 160 and 200 μA/μm in NDGO process due to a difference in the gate oxide thickness at similar boron doses. A 10 year lifetime of thick oxide cell transistors is projected for a V g =8.9 V due to an electrical stress release at the STI top-edge round improved by the pad oxide undercut. The hot carrier lifetime and hot electron induced punchthrough also showed good characteristics. Consequently, this NDGO process is able to provide a reliable transistor performance for a 256M-bit mobile DRAM operating at low power.

Scaling of MOSFET increases the portion of the device channel that is affected by proximity to the shallow trench isolation (STI) trench. Experimental data show that this proximity effect results in a channel-width dependent hot-carrier degradation of pMOSFETs in a 0.25 μm CMOS technology. Device simulations are used to show that electric field differences between the STI edge and center channel region are responsible for the channel-width dependent degradation. Discrete device measurements and product burn-in data are presented to support this explanation of the pMOSFET degradation mechanism.

We present an investigation of local mechanical stress in shallow trench isolation by UV micro-Raman spectroscopy. UV light (364 nm) penetrates only 15 nm into silicon. In contrast to conventional micro-Raman spectroscopy using visible light only the stress very close to the surface is monitored. In this way, local areas of high stress can be detected, that are not seen with longer wavelength light due to averaging. We demonstrate the advantages of the UV method by an investigation of the influence of different trench oxide densification ambients on the amount of mechanical stress in the silicon substrate. We find, that large mechanical stress up to 800 MPa is introduced at the active area edges during densification in steam ambient. This stress is caused by the formation and growth of a bird’s beak, which may lead to defect creation especially in small trenches. This investigation demonstrates the capability to use UV micro-Raman spectroscopy in ULSI technology.

We have investigated the hot carrier reliability characteristics of narrow width MOSFET with shallow trench isolation. In the case of maximum substrate current condition, the lifetime of nMOSFET is slightly degraded by decreasing the device width. However, a significant degradation of device lifetime of the narrow width device was observed under channel hot electron condition ( V g = V d ). In the case of pMOSFET, we also found enhanced degradation of narrow width device under channel hot electron condition. Enhanced degradation of MOSFETs can be explained by both the current crowding and enhanced charge trapping at the shallow trench isolation edge. Considering pass transistor in DRAM cell, the degradation of lifetime for narrow width device under high gate bias condition causes a significant impact on circuit reliability.

MOSFET (metal-oxide silicon field effect transistor) evolution and technology scaling impacts electrostatic discharge (ESD) protection networks, design and strategy. The continous evolution of semiconductor processing forces new issues to arise for each technology generation and the evolution of MOSFET structures in each generation requires re-addressing of the scaling implications on ESD robustness. This paper addresses the impact of semiconductor technology evolution and scaling of the epitaxial film, well design, isolation technology, MOSFET junctions, silicides, and interconnects on ESD robustness. The scaling of the epitaxial film thickness and p++ vs p− substrate influences the ESD robustness of n-channel MOSFET and diode-based ESD protection networks. ESD diode elements show a 2× to 3× improvement in thin p− epitaxy on a p++ wafer compared to p−substrates. The evolution from diffused wells to MeV-implanted retrograde well designs have shown that the parasitic vertical bipolar transistor plays a lesser role in ESD protection networks compared to the diode action. A 3× HBM (human body model) ESD improvement is demonstrated using advanced high dose MeV retrograde well implants. Isolation technology has an influence on the high voltage electrical parametrics, lateral parasitics, thermal transport and semiconductor process integration with the MOSFET junction and silicide film. The transition from LOCOS to STI (shallow trench isolation) significantly altered the electrical parametrics, failure mechanisms, and ESD networks. The MOSFET-junction evolution from Ldd, dual-Ldd, abrupt junctions to “extension implants” and how this influenced integration and ESD robustness is discussed. MOSFET junctions, salicide, and STI integration issues, such as STI pull-down, can influence the ESD robustness of ESD diode structures. Althernative salicide processes (e.g. cobalt), deep B11 implants and novel poly-silicon-bound diode structures demonstrate 3× improvement in HBM ESD robustness. As technology transitions from aluminum- to copper-based interconnect systems, interconnect wire (2× improvement) and via (3× improvement) ESD improvements are demonstrated. As a result of power supply scaling, the impact of technology scaling on ESD networks, peripheral I/O driver circuits and receiver networks, and how it influences the ESD protection of advanced semiconductor chips is shown. Power-supply scaling, noise issues and multichip systems has led to increasing complexity and importance of sequence-independent ESD networks, ESD networks between power supplies and ESD power clamps. Receiver and I/O driver designs have also evolved due to the MOSFET dielectric scaling and ESD robustness requirements. Technology generation evolution of peripheral driver circuits evolution demonstrates the need for local resistor ballasting of driver circuits. With MOSFET scaling, receiver circuit pass transistors, keeper feedback and zero-Vt devices introduce new ESD issues and receiver design complexity. MOSFET scaling requires ESD power clamps across core and peripheral supplies to reduce the current loop impedance for high frequency applications. MOSFET scaling also has led technology to have a future interest in high-frequency semiconductor devices, such as rf-CMOS, silicon-on-insulator, and SiGe-based devices. Novel SOI ESD networks, such as polysilicon-bound diodes and body- and gate-coupled SOI ESD networks, demonstrate excellent ESD results in advanced CMOS-on-SOI technologies.

The in-depth profile of strain distribution from the silicon surface is one of the most important pieces of information for optimizing the device performance. The convergent-beam electron diffraction(CBED) method has been applied to analyze the local strain filed of the active regions for both test structure with the shallow trench isolation(STI) and the conventional LOCOS on a cross-sectional surface. As a result, strain distribution was observed successfully. It was found that the compressive stress exist all over the survey regions. The active region close to the bottom corner of the STI shows a larger stress than that of the conventional LOCOS. It is demonstrated that the CBED technique is very effective for the determination oflocal strain field in a small area of semiconductors and the optimizing of the STI structure andfabrication process.

This paper presents Shallow Trench Isolation (STI) process steps for sub-1/4 μm CMOS technologies. Dummy active areas, vertical trench sidewalls, excellent gap filling, counter mask etch step and CMP end point detection, have been used for a 0.18 μm CMOS technology. Electrical results obtained with a 5.5 nm gate oxide thickness show good isolation down to 0.3 μm spacing. Good transistor performances have been demonstrated.