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Abstract Considering that Elliptic Curve Digital Signature Algorithm (ECDSA) implementations need to be efficient, flexible and Side Channel Attack (SCA) resistant, in this paper, a design approach and architecture for ECDSA and the underlined scalar multiplication operation is proposed for GF (2 k ), satisfying the above three directives. To achieve that, in the paper, Binary Edwards Curves (BECs) are adopted as an alternative to traditional Weierstrass Elliptic Curves (ECs) for GF (2 k ) since they offer intrinsic SCA resistance against simple attacks due to their uniformity, operation regularity and completeness. To achieve high performance and flexibility, we propose a hardware/software ECDSA codesign approach where scalar multiplication is implemented in hardware and integrated in the ECDSA functionality through appropriate drivers of an ECDSA software stack. To increase BEC scalar multiplier performance and introduce SCA resistance we adopt and expand a parallelism design strategy/methodology where GF (2 k ) operations of a scalar multiplier round for both point operations performed in this round are reordered and assigned into parallelism layer in order to be executed concurrently. Within this strategy we include hardware and software based SCA countermeasures that rely on masking/randomization and hiding. While scalar randomization is realized by the ECDSA software stack in an easy way, in order to achieve resistance using hardware means, we propose and introduce in every scalar multiplier round, within the parallelism layers, projective coordinates randomization of all the round's output points. So, in our approach, considering that with the proposed parallelism plan in every scalar multiplier round BEC point operations are performed in parallel and that the round's output points are randomized with a different number in each round, we manage to achieve maximum SCA resistance. To validate this resistance, we introduce and realize a leakage assessment process on BEC scalar multipliers for the first time in research literature. This process is based on real measurements collected from a controlled SAKURA X environment with a GF (2233) based scalar multiplier implementation. Using Welch's t -test we investigate possible information leakage of the multiplier's input point and scalar and after an extended analysis we find trivial leakage. Finally, we validate the ECDSA architecture and its scalar multiplier efficiency by implementing it on a Zynq 7000 series FPGA Avnet Zedboard and collecting very promising, well balanced, results on speed and hardware resources in comparison with other works. [ABSTRACT FROM AUTHOR]

The paper proposes an analog hardware solution for the implementation of two-dimensional gradient-based algorithm. The algorithm employs the discrete cosine transform and performs missing samples reconstruction by using the compressive sensing principles. Although there is a number of algorithms for solving two-dimensional compressive sensing problems, for many of them a real-time application is a challenging task. Therefore, this paper observes an algorithm whose real-time application has relatively low complexity. Also, the reconstruction accuracy is comparable to the commonly used compressive sensing algorithms. The algorithm is observed within the several parts. The implementation of each part is considered in details, with provided discussion on the computational complexity of each part. [ABSTRACT FROM AUTHOR]

In this paper, a novel high speed and efficient area optimal Ate pairing processor implementation over Barreto-Naehrig (BN) and Barreto-Lynn-Scott (BLS12) curves on field-programmable gate array (FPGA) is proposed. The optimal Ate pairing proposed design, based on two steps: Miller loop and final exponentiation, is specifically optimized for FPGA platforms. The Miller Loop and Final Exponentiation algorithms are optimized and modified for careful scheduling to avoid data dependency and to decrease the number of loops and number of temporary variables required for final exponentiation. Furthermore, suitable multiplier combining Toom-Cook and Karatsuba algorithms is proposed to execute the arithmetical computations needed in pairing architecture processor over F p .Therefore, an enhancement in terms of pairing computation speed-up and memory resources capacity management is achieved. In this paper, we select the new pairing parameters, especially that has to be used to ensure the 128-bit security level [1]. The proposed optimal Ate pairing architecture at 128 bits security level has been implemented on Xilinx FPGA Virtex6. Our processor implemented over BN curves achieves the highest reported speed together with the best reported area-time performance on Virtex6 (0.35 ms at 225 Mhz). Finally, for BN-446 and BN-638, the pairing proposed processor performances are estimated. [ABSTRACT FROM AUTHOR]

This paper presents a platform for evaluating sensor data fusion algorithms based on a Network-on-Chip (NoC). Initially the NoC is simulated by MPSoCSim, which contains an ARM and several MicroBlaze processors. The approach is furthermore evaluated on a real FPGA system in an automotive context. Charging stations for electric vehicles consist of expensive sensors, as the energy measurement system is an important part used for billing purposes, for safety of the charging process and for security. The sensors, that are usually used, are special made solutions, which are thermally stable and highly accurate. The NoC infrastructure presented in this paper results in a new method for sensor data fusion, which decreases costs by using inexpensive sensor units. These sensor units are sensitive to temperature changes. The target of the sensor data fusion approach is to replace expensive sensors with inexpensive ones without loosing accuracy. The presented simulation platform allows an easy exchange of sensor models and sensor data fusion algorithms. [ABSTRACT FROM AUTHOR]

The design and implementation of eight novel non-cryptographic hash functions is proposed in this paper. Those can suitably be employed in networking and security applications that require fast lookup and/or counting architectures. Our approach is inspired by the design of the existing non-cryptographic hash function Xoodoo-NC, which is constructed through the concatenation of several Xoodoo permutations. In a similar way, this work concatenates several rounds of symmetric-key ciphers to construct non-cryptographic hash functions. The goal is to achieve high performance while maintaining the avalanche properties. Meeting the avalanche criteria is necessary to yield a significant change in the output of hash functions even for the slightest change in the input. The number of rounds required to achieve satisfactory avalanche scores for each cipher is simulated. We implement the corresponding non-cryptographic hash functions on an FPGA and we synthesize them on ASIC to evaluate the occupied resources and the performance. This paper evaluates the performance and area of ASIC implementations optimized for high operating speed. This evaluation is done on the 65 nm TSMC technology. One of the proposed non-cryptographic hash functions, namely PHOTON-NC, outperforms all previously proposed non-cryptographic hash functions in terms of throughput and latency on FPGA, in exchange for an acceptable increase in FPGA resources, while Xoodoo-NC proves to have the highest performance on ASIC. [ABSTRACT FROM AUTHOR]

Recent years have seen an increasing number of scientists employing data parallel computing frameworks, such as Hadoop, in order to run data-intensive applications. Research on data-grouping-aware data placement for Hadoop has become increasingly popular. However, we observe that many data-grouping-aware data placement schemes are static, without taking MapReduce job execution frequency into consideration. Such data placements scheme will lead to severe performance degradation that is way below the potential efficiency of optimal data distribution when executing MapReduce jobs that are executed frequency. In this paper, we propose a new data-grouping-aware dynamic (DGAD) data placement method based on the job execution frequency. Firstly, we build a job access correlation relation model among the data blocks according to the relationships provided by the records about historical data block access. Then we use a clustering algorithm to divide data blocks into clusters according to the job access correlation relation model among the data blocks and propose a data placement algorithm based on data block clusters in order to put correlated data blocks within a cluster on the different nodes. Finally, a series of experiments are carried out in order to verify the method proposed in this paper. Experimental results show that the proposed method can effectively deal with the mass data and can obviously improve the execution efficiency of MapReduce. [ABSTRACT FROM AUTHOR]

• Numerical methods used for the estimation of the RMS. • Simpson's 1/3 rule and Simpson's 3/8 rule modified for the purpose of general application. • Modified Simpson's rules do not necessitate more complex mathematical calculations than those used in the existing methods. • Modifications provide better measurement results for some a lower ratio of the frequency of sampling and the frequency of the signal. • Modified methods do not require the manufacturers of commercial measurement equipment to additionally invest in it. This paper demonstrates that direct changes in the algorithm for the estimation of the root mean square value of a voltage signal of an arbitrary waveform can lead to improved performances and lower measurement uncertainty of commercially available instruments without requiring any upgrade of their existing hardware. The research conducted and presented here is an original contribution to the development of estimation techniques and mathematical models for measurement oriented purposes regardless of the number of samples in the given period relying on mathematical calculation of the equal complexity as in the methods already in use. The theoretical approach examines the problem of numerical integration focusing on modified Simpson's 1/3 rule and modified Simpson's 3/8 rule used for the purpose of the estimation of the root mean square value when a small number of samples per period is available. It highlights the limitations of Simpson's 1/3 rule and Simpson's 3/8 rule, and shows that the newly proposed algorithm is optimal with respect to measurement accuracy and precision even in cases when the ratio of the sampling frequency and the signal's fundamental frequency is low. All theoretical results have been validated experimentally. [ABSTRACT FROM AUTHOR]

The Whale Optimization Algorithm (WOA) is a new advanced algorithm that is based on the humpback whale chasing process. The main problem addressed by Whale Optimization Algorithm, similar to other metaheuristic algorithms, is premature convergence. This paper introduces the Sine Cosine Algorithm in the Whale Optimization Algorithm optimization process to enhance global convergence and to improve enactment. The proposed algorithm, called WOA-SCA, has local optima evasion of Whale Optimization Algorithm and high capability to increase the exploration. The implementation of the proposed WOA-SCA algorithm is investigated through a series of tests on common benchmark test functions, with the results compared to those of six alternative algorithms. The results of the investigations show that the proposed WOA-SCA algorithm works better in concert with the outputs of the benchmark functions. Also, to validate the proficiencies of the WOA-SCA, it has been used to resolve the real-world problem of Facial Emotion Recognition (FER). The field of facial emotion recognition is a fascinating new area of research that gives us the ability to identify the human face's expression in natural settings. A large part of the standard methodologies certainly does not indicate the looks because the attitudes depend on the human face sections' behaviors. The paper proposes the efficient Facial Emotion Recognition method using MultiSVNNN based on WOA-SCA (the proposed WOA-SCA based Multi-Support Vector Neural Network). Using the ADFES dataset for the disgust expression, our results demonstrate that the proposed work yields average emotion recognition accuracy of 98% associated to 80% and 96% based on BBPSO and MFOPSO, respectively. Investigational consequences indicate the virtuous enactment of the proposed scheme resolutions regarding precision. [ABSTRACT FROM AUTHOR]

This paper presents design of novel embedded computational architectures for real time, in-motion mapping based on ultrasound sensors for use in resource constrained autonomous rovers. Autonomous rovers are a class of real time systems that are constrained for size, weight, on-board computational resources and power. Embedded computing architectures designed for implementing the mapping and navigational algorithms must optimize the use of these resources. In the process of map generation, raw sensor data obtained from an array of ultrasound sensors is filtered for sensor noise using probabilistic sensor model, and probabilistic data fusion methods are employed for spatial and temporal correlation of data for improving the map. In this paper, we present a System-on-Chip design based design space exploration of embedded computational architectures for implementation on field programmable gate arrays. We seek to exploit system level, region level and sensor level parallelism in the mapping algorithm for enhancing the throughput. Design space exploration is carried out by employing existing soft core processors, designing custom co-processors and data path modules and integrating them using parallel and pipelined data flow approaches. Results of mapping a test area on all the architectures are compared to characterize the performance and suitability of the proposed architectures. [ABSTRACT FROM AUTHOR]

High level security is always an important requirement to save the sensitive information traveled across the MANET-IoT. Secure routing is one of the major concerns to prevent impersonation attacks from the network. There are many state of the art routing model available based on trusted metrics to enhance the security of the MANET-IoT. However, still there are many challenges to provide high secure environment due to the dynamic characteristics of the network. In this paper, an enhanced multi attribute based attack resistance (EMBTR) algorithm is proposed to perform the routing process securely based on nodes' trusted values. The work proposed here uses QoS parameters such as stability rate (SR), reliability rate (RR), and elapsed time (ET) to enhance the performance of the network by combating trust related attacks. The algorithm introduced in the paper can provide a trustworthy route by isolating the misbehavior nodes from the communication path based on the trusted metrics calculated for the nodes in the network. The proposed work is compared with currently available routing algorithms such as TSRM (Trust based secure routing model), and TARF (Trust-aware routing framework for WSNs). The result shows that the proposed work can efficiently detect and remove malicious nodes from the network and provide secure routing with limited energy, and high detection rate than the currently available solutions. [ABSTRACT FROM AUTHOR]

Abstract: A scalable elliptic curve cryptography (ECC) processor is presented in this paper. The proposed ECC processor supports all five Koblitz curves recommended by the National Institute of Standards and Technology (NIST) without the need to reconfigure the FPGA. The paper proposes a finite field arithmetic unit (FFAU) that reduces the number of clock cycles required to compute the elliptic curve point multiplication (ECPM) operation for ECC. The paper also presents an improved point addition (PADD) algorithm to take advantage of the novel FFAU architecture. A scalable ECC processor (ECP) that is completely implemented in hardware that makes use of the novel PADD algorithm and FFAU is also presented in this paper. The design is synthesized and implemented for a target Virtex-4 XC4VFX12 FPGA. It uses 2431 slices, 1219 slice registers, 3815 four-input look-up tables (LUT) and can run at a maximum frequency of 155.376MHz. The proposed design is the fastest scalable ECP that supports all five Koblitz curves known to the authors as it evaluates the ECPM for K-163 in 0.273ms, K-233 in 0.604ms, K-283 in 0.735ms, K-409 in 1.926ms and K-571 in 4.335ms. The proposed design is suitable for server-side security applications where both high-speed and scalability are important design factors. [Copyright &y& Elsevier]

Abstract Detection of underground objects remains an important task today, particularly when attempting to recover landmines. A Ground Penetrating Radar (GPR) sends short pulses in time domain to detect underground objects by recording the reflected signal. GPR traces acquired at different positions in space are combined together to form B-scan images. The presence of objects produce hyperbolic fluctuations in B-scan images that depend on the shape, dielectric properties, and depth of the sensed object, and also on the properties of the medium. Dielectric properties of some objects, like plastic objects, create very small fluctuations in GPR traces. To analyze the recorded patterns, efficient algorithms need to be developed and improved based on the inherent variations of the overall conditions. For detecting underground objects under noise, this paper compares the results of two algorithms: Histograms of Oriented Gradients (HOG), and n-Row Average Subtraction (nRAS). For tests, five different scenarios from two test configurations have been used. According to the results for all images in the first test configuration, HOG and 3RAS algorithms both increase Object Detection Ratio (ODR) from 88% to 93% while decreasing the False Alarm Rate (FAR) considerably. The accuracy is also tested for different image sizes. And for certain algorithms, lower resolution images result in better accuracy. [ABSTRACT FROM AUTHOR]

Abstract This paper presents an architecture-aware Progressive Edge Growth (PEG)-based construction method for Low-Density Parity-Check (LDPC) codes. We target optimization through code construction for layered architectures with pipelined processing and memory organized in single-port banks. For a given layered Quasy-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture configuration, the code constraints need to maximize hardware usage efficiency. Implementation results for Field-Programmable Gate Array (FPGA) technology suggest that the codes obtained using the proposed algorithm have a throughput increase of 39% up to 110%, due to the increase in working frequency obtained by using pipeline. [ABSTRACT FROM AUTHOR]

Abstract The aim of this paper is to present two different architectures for evaluating individual or group stress levels. First, the cloud architecture is presented in which a client device is used simply to detect an ECG (electrocardiographic) or PPG (photoplethysmographic) signal and transmit it in raw form to a server, where all the signal processing and evaluation is then carried out. The second architecture consists of a stand-alone client device that measures the signal and also performs signal processing, indicating the level of stress. Here the server merely receives the processed data and is mainly used to perform additional data analysis while providing a platform to show the stress (and other) evaluation results. We compared both architectures regarding the amount of data transmitted between the client and the server, the power and memory consumption of the client, and accuracy of the QRS algorithm detection where QRS refers to the heart's ventricular depolarisation and is represented by three deflections observed on a typical electrocardiogram. The QRS detection algorithms were tested with the MIT-BIH Arrhythmia Database and real-life data. The results indicate the accuracy of the QRS detection on the stand-alone device compared to that on the server side. A hybrid approach is more user-friendly because the stress-level results are displayed directly by the device rather than by an additional device such as a smart phone, whereas the server side allows for the long-term analysis of stress levels. These two client devices also have comparable prices, although the price of the stand-alone device is somewhat higher due to the graphical stress-level indicators. Therefore, we propose the hybrid approach when one is seeking a high-quality, miniature and low-cost solution that directly shows the stress level in real-time. [ABSTRACT FROM AUTHOR]

Abstract This paper presents a new algorithmic approach to construct a generic N th Order Walsh Functions (WF) using Transition Sequence (TS). The TS acts as a pointer to the desired Walsh Index (WI) and produces the Sign Change string (S). This string becomes input to a triggered flip flop to generate 2n Walsh Sequences (WS). The proposed strategy totally removes the obvious use of modulo 2 adders leading to a simpler Isomorphic architecture. The FPGA implementation of the generated WS shows a superior performance for higher order WF (n) up to 9. This novel approach reduces Hardware (HW) area by 25–90% and Dynamic Power (DP) by 3–60%, with varying n from 4 to 9, as compared to pure sequential design approach. The proposed design has been tested and verified on the Xilinx Virtex-5 platform. [ABSTRACT FROM AUTHOR]

Abstract Crosstalk faults occurring in wires of Networks on Chip (NoCs) can seriously threaten the reliability of data transfer. One efficient way to tackle crosstalk faults is numeral-based Crosstalk Avoidance Codes (CACs). Numeral-based CACs reduce crosstalk faults by preventing specific transition patterns to occur. One-Lambda Codes (OLCs) are the most efficient types of CACs. However, the codec of OLCs imposes overheads including power consumption, critical path and area occupation to the routers of NoCs. To find overhead-efficient OLCs, this paper proposes an Algorithm for Generating OLC Numeral systems (AGON). AGON provides a tradeoff for designers in selecting overhead-efficient OLCs. Using AGON, an efficient numeral-based OLC called Subtraction-based-Numeral (Sub-Num) is proposed that benefits the Numeral system that can omit OLC-induced transition patterns completely. In addition, the mapping algorithm of Sub-Num can reduce the overheads of codec more efficiently than the other state-of-the art OLCs. Evaluation results using SPICE and VHDL simulations show that Sub-Num reduces power consumption and average delay of wires by 10% and 9%, and also overheads of codecs including dynamic power consumption, critical path and area occupation by 52%, 51% and 21%, respectively as compared to the state-of-the-art numeral-based OLC. [ABSTRACT FROM AUTHOR]

Abstract: Partial Runtime Reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. We make two contributions in this paper. First, we present an efficient algorithm for finding the complete set of Maximal Empty Rectangles on a 2D PRTR FPGA. We also present a HW implementation of the algorithm with negligible runtime overhead. Second, we present an efficient online deadline-constrained task placement algorithm for minimizing area fragmentation on the FPGA by using an area fragmentation metric that takes into account probability distribution of sizes of future task arrivals as well as the time axis. The techniques presented in this paper are useful in an operating system for runtime reconfigurable FPGAs to manage the HW resources on the FPGA when HW tasks that arrive and finish dynamically at runtime. [Copyright &y& Elsevier]

Abstract: In a highly connected World, network security is a must even for embedded systems. However, cryptographic algorithms are computationally intensive and the processors used in FPGA-based embedded systems are known to have a modest performance. In fact, this paper presents a study showing that unless HW acceleration is used, the throughput of secure applications on FPGA-based embedded systems is poor when compared to the current networking standards. But the multi-algorithm nature of most applications poses many difficulties to classic HW acceleration, particularly large area utilization and difficulty in supporting new algorithms. Fortunately, these problems can be easily solved using partial run-time reconfiguration. This paper proposes an architecture based on self-reconfiguration that allows the implementation of hardware accelerated secure applications in FPGA-based embedded systems. Cryptographic coprocessors are efficiently deployed without incurring in the problems mentioned above, and moreover, without needing any external components. To prove the feasibility of this proposal, a proof-of-concept implementation of the well-known SSH application has been developed in a low-cost commercial device running a standard operating system. [Copyright &y& Elsevier]

Abstract: The CORDIC (coordinate rotation digital computer) algorithm is an iterative technique that can be used to compute many arithmetic functions using mainly shifts and additions making it ideal for FPGA implementation. In the early 1990s, Yu Hen Hu developed an equation for the overall quantisation error (OQE) experienced by the CORDIC algorithm when computing a vector magnitude. This equation could be used to find the most efficient architecture that would give a desired level of accuracy thus avoiding a trial and error approach. In this paper, we note that in fact the OQE overestimates the error in many cases, thus yielding inefficient architectures. Hence, this paper presents an updated equation for the OQE which is more accurate in predicting the error. To illustrate the improved accuracy of the new OQE expression, comparisons are made between CORDIC systems found using both versions of the OQE algorithm and Direct systems computing a vector magnitude. This comparison is of interest as it shows that CORDIC systems based on the new OQE expression use considerably fewer FPGA resources than CORDIC systems found using the original algorithm or equivalent direct designs. Given the widespread use of CORDIC in FPGA designs, particularly in DSP, this is significant. [Copyright &y& Elsevier]

The paper suggests a novel method for implementing recursive algorithms in hardware. The required support for recursion has been provided through a modular and a hierarchical specification of a control unit that can be translated to an implementation of the respective hardware circuit on the basis of a recursive hierarchical finite state machine and through a mechanism that permits the contents of an execution unit to be stored/restored between hierarchical calls/returns. The paper describes all the details that are required to implement recursive algorithms in hardware. It begins with software (C++) models and finishes with synthesizable VHDL codes. Two practical applications of recursive algorithms in the data sorting and compression area have been studied in detail. [Copyright &y& Elsevier]

In today's world, the demands for high-performance computing necessitate faster on-chip communication. Current chips with a large number of on-chip elements need an efficient alternative such as network-on-chip (NoC) for on-chip communication. As technology down scales toward the deep sub-micron, process variability makes the transistors more unreliable. Hence, on-chip elements including NoC can suffer from permanent/transient failures. In an NoC, 1-link/1-router failure can disrupt overall connectivity. The paper presents an improved routing reconfiguration algorithm for handling all 1-point permanent failures in 2D mesh NoC. By 1-point failure, we mean a failure can be occurred on any network link/router. State-of-the-art approaches either require a large number of reconfiguration cycles or provide partial support for 1-point failures, i.e., cover only 1-link failures. Proposed approach performs partial reconfiguration of routing function implemented using logic-bits instead of costly routing tables, thus reducing hardware overheads for larger networks as well. In terms of performance, the average flit latency cycles are reduced up to 31% and the average network throughput is improved up to 14.5% for 1-router failure in 8 × 8 2D mesh NoC. For 2-router failures, the improvements are 20% and 13% in terms of average flit latency cycles and average network throughput, respectively. [ABSTRACT FROM AUTHOR]

The HypErspectraL Imaging Cancer Detection (HELICoiD) European project aims at developing a methodology for tumor tissue classification through hyperspectral imaging (HSI) techniques. This paper describes the development of a parallel implementation of the Support Vector Machines (SVMs) algorithm employed for the classification of hyperspectral (HS) images of in vivo human brain tissue. SVM has demonstrated high accuracy in the supervised classification of biological tissues, and especially in the classification of human brain tumor. In this work, both the training and the classification stages of the SVMs were accelerated using Graphics Processing Units (GPUs). The acceleration of the training stage allows incorporating new samples during the surgical procedures to create new mathematical models of the classifier. Results show that the developed system is capable to perform efficient training and real-time compliant classification. [ABSTRACT FROM AUTHOR]

The increasing on-chip temperature has become a critical issue in the multiprocessor system on chip (MPSoC). It does not only disturb the reliability and performance of the system but it also increases the power consumption. Load balancing is a common scheduling technique to address the thermal issues where the load is transferred to relatively less used cores. However, during the transfer of workload, the destination cores may be in sleep mode and thus take some time to switch to the running mode. It results in wastage of some processing time. This paper presents a thermal-aware load balancing technique that avoids thermal emergencies while eliminating the switching delays. The proposed technique estimates the time taken by a task set to reach the temperature threshold values with the help of offline recorded thermal profiles of datasets. Moreover, cores are selected in a round-robin manner to equilibrate thermal gradients. The technique is based on Global Earliest Deadline First (GEDF) scheduling algorithm and considers ambient temperature, thermal cycles and energy consumption. The proposed technique is tested in a simulation environment comprising of scheduling and thermal simulation model. The results show that the technique reduces the average temperature up to 17%, thermal cycles up to 15%, energy consumption up to 20% and lowers the temporal and spatial gradients as compared to the commonly used predictive thermal-aware and thermal balancing techniques. [ABSTRACT FROM AUTHOR]

• A real-time application for secure data transmission using a different approach. • The receiver system requires a confirmation signal to perform necessary action. • Utilizing chaos dynamics for generating secret codes used in the algorithm. • The transmitted data can be a simple bit or any multimedia data of major systems. In today's technology, remote control or access is widely used in many platforms. However, the fact that remotely controlled platforms are open to external attacks or not secure enough which can have serious negative consequences. In this paper, a real-time LoRa modulation based data transmission application is achieved. The security of remotely transmitted data is not only provided with a basic encryption structure, but also a confirmation signal based transceiver system is designed in which the required process is performed only with a certain time interval. Firstly, the data to be transmitted is mixed with a secret key using XOR operation then transmitter creates a random period of time that specifies how long after the confirmation signal will be sent relative to the data signal. Hence, the entire system security is enhanced by the timing algorithm running with millisecond precision between the transceiver circuits. Encryption of the confirmation signal in a similar structure as the data signal improves security of the entire system. In this application, a PWM signal containing voltage information has been successfully transmitted in ciphered form using LoRa modulation. The designed algorithm for the receiver and transmitter circuits has been tested and verified in real time application. Experimental results show that the proposed scheme can be applied to any application-based communication system. [ABSTRACT FROM AUTHOR]

FrequentItemsetMining (FIM) is one of the most important data mining tasks and is the foundation of many data mining tasks. In Big Data era, centralized FIM algorithms cannot meet the needs of FIM for big data in terms of time and space, so Distributed Frequent Itemset Mining (DFIM) algorithms have been designed to meet the above challenges. In this paper, LocalGlobal and RedistributionMining which are two main paradigms of DFIM algorithm are discussed; Two algorithms of these paradigms on MapReduce named LG and RM are proposed while MapReduce is a popular distributed computing model, and also the related work is discussed. The experimental results show that the RM algorithm has better performance in terms of computation and scalability of sites, and can be used as the basis for designing the DFIM algorithm based on MapReduce. This paper also discusses the main ideas of improving the DFIM algorithms based on MapReduce. [ABSTRACT FROM AUTHOR]

This paper introduces harmonic removal in a Switched capacitor multilevel inverter utilizing artificial bee colony (ABC) method. The main focus is to neglect lower order harmonics by resolving nonlinear equation. In our paper, ABC algorithm is enforced to a twenty nine level inverter for resolving the equation. Selective Harmonics Elimination PWM is mainly used in lower order harmonics suppression. The MLI gets input from the SEPIC converter that comprises of Photo Voltaic Module as a source of generation. The PV panel output voltage is maintained constantly with a greater gain DC-DC SEPIC converter. Hence to obtain high power from the PV system, gray Wolf Optimization technique and fuzzy logic control is used. The high frequency modulation technique i.e. Multi Carrier modulation technique is too applied in the proposed new topology for reducing the higher order harmonics. The proposed ABC harmonics elimination technique is also compared with genetic algorithm based SHE method. MATLAB simulation platform is utilized to simulate the module. The experimental verification of the proposed work was done using DSPIC30F2010 controller. [ABSTRACT FROM AUTHOR]

As a hotspot of machine learning research, deep learning is applied in many fields. Embedded systems are becoming more and more complex and networked, so the real-time performance of embedded systems and the security of network embedded devices face severe challenges. Based on this, this paper studies the real-time task scheduling problem for complex embedded systems and the security of embedded network devices. For real-time, this paper proposes a comprehensive task scheduling algorithm. Based on the task classification in the embedded system, different scheduling methods are adopted for different tasks, and the scheduling mode is flexibly changed as the system load changes. A dynamic integrity measurement model is established based on the star trust chain structure, and the hardware implementation mechanism of constructing dynamic trust chain in embedded system is studied. The dynamic reconfigurable hardware design method based on FPGA is applied to the construction of dynamic trust chain, and a verification system is designed to verify the dynamic measurement mechanism. This can solve the security problem of deep network embedded devices to a certain extent. [ABSTRACT FROM AUTHOR]

Wireless Sensor Networks (WSNs) include small battery-based self-governing devices that are deployed in a distributed manner to supervise the environmental or physical circumstances. The routers and gateways are connected to the deployed nodes to support many real-time applications. Due to open access, the security issue arises in WSN. In this circumstance, the external users can be verified by securing authentication is necessary one. In real-time applications, to achieve secured communication they have made many lightweight authentication mechanisms. But WSNs are highly susceptible to DoS attacks as it lacks the synchronization between nodes during data routing. In this paper, a new lightweight DoS detection scheme Deep Learning-based Defense Mechanism (DLDM) has proposed to detect and isolate the attacks in Data Forwarding Phase (DFP). This paper describes the new algorithm for the successful detection of DoS attacks, such as exhaustion, jamming, homing, and flooding. We conduct extensive simulation experiments that can accurately isolate the adversaries and it is more resilient to DoS attacks. Our proposed simulation result shows that it can achieve a high detection rate, throughput, packet delivery ratio, and accuracy. This also reduces the energy consumption and the false alarm rate. [ABSTRACT FROM AUTHOR]

The paper presents theoretical background of a new concept of logic synthesis for LUT–based FPGAs. The idea of multi-output function description in the form of PMTBDD diagram is proposed. This form enables to carry out a simple analysis of multi-output function by appropriate algorithms which are dedicated to single-output functions. The essence of logic synthesis is searching for suitable PMTBDD cuttings. The choice of the PMTBDD cuttings enables to obtain an adequate decomposition path. As the result of BDD diagram cutting, SMTBDD diagrams are created. These diagrams are a generalized form of SBDD and MTBDD diagrams. The idea of choosing a cutting line, which matches LUTs included in FPGAs, is also proposed. The essence of the suggested method of searching for the best technology mapping is based on an analytical description of the efficiency of mapping. The experimental results, which prove efficiency of the proposed methods, are presented too. [ABSTRACT FROM AUTHOR]

In recent years, indoor localization has become a hot research topic and several researchers have paid attention to design accurate 3-Dimensional (3D) indoor localization techniques. Existing localization techniques cannot be sufficient for 3D indoor localization due to the existence of interferences and the need for high precision. The most widely used option for outdoor localization is known as the global positioning system (GPS), and its precision in location is often within a 10-meter margin of error. Problems arise in the "final mile" of the localization field due to the complicated impediments that buildings provide, which encourages a momentum of indoor localization. Traditional methods of indoor localization are either dependent on range or fingerprinting, which means that the predeployment process takes a significant amount of time and work to complete. The non-line of sight propagation due to the building shielding and background interferences results in high error on the application of Ultra-Wideband technologies to indoor localization. For resolving this issue, this paper presents a novel group teaching optimization algorithm with improved Chan-Taylor algorithm (GTOA-ICTA) for 3D indoor localization. The GTO-ICTA technique initially employs the GTOA for transforming the target problem into the target of variations among the determined and original positions. Besides, the ICTA technique is employed for computing the accurate positions of the targets. The integration of GTOA and ICTA techniques helps to properly achieve maximum localization performance. For validating the enhanced performance of the presented GTOA-ICTA technique, a set of simulations were performed and the results are examined interms of different aspects. A comprehensive results analysis of the proposed GTOA-ICT technique takes place in positioning error with the minimum error of 0.1245, and the proposed method has reached increased results with the maximum error of 0.9660. Moreover the GTOA-ICT has obtained minimum average error of 0.6432, least Standard deviation of 0.4387. The resultant experimental outcomes highlighted the enhanced performance of the GTOA-ICTA techniques over the recent state of art techniques interms of different measures. [ABSTRACT FROM AUTHOR]

With the Internet of Things, an increasing amount of sensitive data have to be communicated and hence encrypted. Low-cost hardware attacks such as fault analysis or side-channel analysis threaten the implementation of cryptographic algorithms. Many countermeasures have been proposed against either of these attacks, however, only a few countermeasures protect efficiently an implementation against both attacks. These joint countermeasures usually have a prohibitive area and power overhead, and require up to thousands of bits of fresh randomness at each encryption. Therefore, they may not be suited to protect lightweight algorithms in resource-constrained devices. In this paper, we propose a new joint countermeasure against both attacks, called dynamic encoding. It has a smaller power and area overhead than existing joint countermeasures and requires at most 8 random bits at each encryption. It is particularly adapted to protect sequential logic and lightweight algorithms based on shift registers, and it can be extended to protect combinational logic as well. It consists in a power balancing at algorithmic level and provides an inherent fault detection. Simulations with several levels of noise indicate that dynamic encoding provides an efficient protection against side-channel analysis with up to 100,000 traces. • Lightweight joint countermeasure against side-channel and fault analysis. • Power balancing without precharge, with inherent fault protection. • Side-channel leakage evaluation of power balancing in presence of noise. • Security of an hardware implementation of the stream cipher Trivium. [ABSTRACT FROM AUTHOR]

In recent years, algorithms based on human pose estimation have been applied more and more in low power embedded system. However, the keypoints detection under occlusion is not well solved, resulting in poor effect in practical application on embedded devices. In this paper, we propose a novel Simple and Effective Network (SEN) to deal with the multi-person pose estimation problem of low power embedded system via detecting occlusion keypoints quite well to a certain extent. This model is easy to apply to embedded devices, and has the characteristics of simplicity, strong expansibility and wide application, which are very important in the world of Internet of things. Our model contains three novel modules: Feature Fusion Module (FFM), Channel Enhancement Attention Module (CEAM), and Feature Enhancement Module (FEM). The FFM fuses the shallow and deep feature maps, bringing rich context information to the model. At the same time, it can alleviate the problem of information loss caused by downsampling operations and locate the keypoints more accurately. The FEM and the CEAM act on the deep feature maps of the network, which helps to infer the keypoints of occlusion or invisibility. Related experiments explain that the raised means is effective and achieves the superior performance over two benchmark datasets: the COCO keypoints detection dataset and the MPII Human Pose dataset. [ABSTRACT FROM AUTHOR]

Both the one-dimensional method based on vector and the two-dimensional method based on matrix in image feature extraction are only suitable for the processing of small scale images. In this paper, we improved the (2 D ) 2 PCA algorithm based on image block. In addition to the conventional correlation method, we proposed three methods: image enhancement processing method, image block method and the method of creating projection matrix based on local mean and standard deviation. We also presented the executive process of the (2 D ) 2 PCA algorithm on the MapReduce programming model and compared its performance in terms of the stand-alone machine and cluster environment. The experiment results showed that the (2 D ) 2 PCA algorithm based on image block has higher execution efficiency, better speedup, better scalability and is suitable for massive image data processing. [ABSTRACT FROM AUTHOR]

In this paper, we present a uniform acceleration framework for GPU-based interactive visualization of regular scalar fields. Firstly, in order to exploit the coherence of volume fields in both the object space and the image space, we propose a general bi-space rendering proxy (BSRP) to represent volume fields. These BSRP are organized into pointerless tree structures which can index voxels in a multi-scale manner. Based on BSRP, we present a novel multi-scale stream reduction (MSSR) algorithm to rapidly process BSRP-indexed valid voxels (i.e., active voxels in marching cubes or nonempty space in volume raycasting). In the object space, MSSR utilizes pre-computed tree structure to rapidly get rid of invalid voxels using multi-scale BSRP with minimal overhead, and thus can noticeably reduce the complexity of classification, scan and compaction for valid voxels. In the image space, given view parameters, the BSRP containing valid voxels are rasterized in a coarse-scale. Then, MSSR expands them as lossless ray segments for volume raycasting, where both the exterior and interior empty space are skipped. Our framework addresses the acceleration problem by decomposing volume rendering algorithm into several data-parallel stages processing multi-scale stream, which are mapped efficiently to the massively parallel architecture of modern GPUs. Thanks to the proposed MSSR algorithm, our framework is immune to the changes of iso-value, transfer function and view parameters, which is especially efficient in scenarios requiring frequently interactions. Experimental results demonstrate that the performance of our framework outperforms state-of-the-art algorithms. [ABSTRACT FROM AUTHOR]

A GPGPU is very important technology and a research hotspot for cloud computing. We pay close attention to its energy consumption and performance. In this paper, a static performance analysis model of GPU, SKE (Single Kernel Estimate), is set up to analyze the completion time of the kernel function on a GPU to find the optimal parallel solution to different tasks in a specific GPU device and the granularity size of the thread-block division, thus enabling the fastest execution speed of the kernel function. The deviation between the completion time calculated by SKE and the real execution time of the kernel is no more than 13%. On this basis, we calculate the completion time for each sub-GPU task and seek the critical path of the GPU cluster, and propose a GPU cluster scheduling algorithm, BCS (Based on Critical-path-Scheduling). The algorithm regulates the frequency of non-critical nodes, mainly through dynamic voltage and frequency scaling (DVFS) technology, and achieves the goal of reducing the energy consumption of GPU nodes without affecting the final completion time of the cluster. The evaluation results show that BCS reduces energy consumption by a maximum of 9.4%, compared to DRS. [ABSTRACT FROM AUTHOR]

Among instances when the data and image security in resource constrained environment (smart devices and the like) are to be taken into consideration, lightweight encryption algorithms accede in popularity and are deemed of to be of great merit. In devices as those of the sort mentioned, reducing both power consumption and gate count is always a prime concern. LEA, therefore, triumphs on merit, owing to its low consumption levels of hardware resources, which itself is a result of the adaption of simple modular addition, bitwise rotation and bitwise XOR (ARX) operation instead of the relatively more complex S-box technique. The algorithm in question supports keys of varying sizes three, to be precise: 128, 192 and 256-bit for the intent of providing three levels of image and data security. The hardware implementation of the LEA algorithm for the varying key sizes as mentioned above share significant kinship and hardware resources. This paper puts forward the proposition regarding a high speed low area unified architecture for LEA algorithm for three different sizes of key. The individual hardware implementations of the three key sizes tend to consume more hardware resources than those involved in the proposed unified architecture. The pipelined implementation of the proposed design improves operating frequency to a significant degree, with a little increase in the hardware costs. The design proposed in this paper notably supports three varying tile sizes, i.e. 256 × 256 , 128 × 128 , 64 × 64, of an input image. As resolution of an input image may not necessarily be an integer multiple of the size of tile, smaller tile sizes at the image boundary can also be handled by the same architecture. The design hereby proposed has been implemented on both UMC ASIC 0.09- μ m and XC5VLX330T FPGA platforms and achieved maximum operating frequencies of 740 MHz and 292 MHz respectively. As its increasingly evident on account of the FPGA implementation outcomes, the proposed unified architecture results in vastly improved levels of operating frequency (34%, 33% and 131%) as opposed to the individually available LEA architectures (corresponding to three different key sizes: 128, 192 and 256-bit, respectively). Proposed architecture shows 28%, 35% and 45% increment in the hardware resources with respect to available LEA architectures with single key. The incorporation of the unified key generation technique and pipeline implementation of the algorithm are the main reasons for the more hardware utilization. [ABSTRACT FROM AUTHOR]

This paper proposes a design of a fast FPGA based architecture for Coordinate Rotation Digital Computer (CORDIC) algorithm with reduced number of iterations. CORDIC is on such technique which uses just shift-add/sub operations. So, it widely has been used because its flexibility characteristics. However, the major disadvantage is its relatively slow computational speed due to the determination of rotation direction by analyzing the results of the previous iteration. The basic idea of this paper is to reduce the iteration number to overcome this shortcoming. Finally, the prototype based on FPGA architecture has been established to test the performance of the proposed design. The design is implemented in VHDL, synthesized on Xilinx Spartan6 xc6slx9-2tqg144 FPGA kit. The proposed architecture computes Sine and Cosine values in 3/8 n ( n is the bit-width of operand) clock cycles and the maximum operating frequency of the proposed architecture is as fast as 108.120 MHz. The simulation and implementation results verify the authenticity of this design. [ABSTRACT FROM AUTHOR]

Brain Storm Optimization (BSO) is a metaheuristic algorithm that has been gaining attention in solving engineering problems. The algorithm emulates the human brainstorming procedure by initializing a population and optimizing it over several generations. The algorithm enjoys intrinsic parallelism that enables the development of high-speed hardware implementations. However, investigations on accelerating the BSO are yet limited in the literature. In this paper, we present a parallel BSO processor under Field Programmable Gate Arrays (FPGAs). The development includes sequentially modeling the algorithm, deriving parallel versions, targeting a rich set of benchmark evaluation functions, and performing thorough validations. The results confirm the achievement of appealing performance characteristics that significantly outperform software implementations in terms of execution speed. The paper includes thorough analysis, evaluation, and sets the ground for future works. [ABSTRACT FROM AUTHOR]

Dynamic Range Compression (DRC) algorithm helps to protect the residual hearing ability of hearing aid users by compressing the signal levels which go above a particular threshold. This paper addresses two different aspects of DRC for hearing aid applications. In the first part, methods to estimate the decay coefficients corresponding to the required time constants for a feed-forward DRC architecture accurately, to meet the hearing aid specifications are proposed. The effect of compression on the attack and release time parameters are compensated with the new formula. The hardware implementation of four different DRC architectures is explained in the second part of the paper. The estimated decay coefficients for a test signal were used for the corresponding hardware implementations and verified the validity of proposed algorithmic modifications. The architectures were implemented using UMC 65 nm standard cell libraries and the power and error results were compared. The proposed methods to estimate the decay coefficients for both attack and release phases show close to 0 dB error from expected output values, while conventional methods are not meeting the specifications. Hardware implementation shows that there is not much improvement in power performance, between a lower resolution Look-Up Table (LUT) based logarithm implementation and a higher resolution one. From the results, we propose using the absolute level detector based DRC with higher resolution logarithm without a gain smoothing stage at the output for lowest power consumption and better approximation error performance. [ABSTRACT FROM AUTHOR]

In this paper, we propose an online security-aware hardware scheduler, the so-called Secure And Fast hardware Scheduler (SAFAS), for real-time task scheduling in multi-core systems in the presence of schedule-based side-channel attacks. To avoid such attacks and ensure that all tasks meet their deadlines, SAFAS schedules critical tasks and their replicas using a hardware-based strict Least Slack Time first (LST) algorithm independently while it independently schedules the non-critical tasks using a hardware-based EDF algorithm. SAFAS enhances the system performance and reduces the chance of side-channel attacks due to the different processing cores allocated to each task in each scheduling interval. The hardware scheduler operates independently and in parallel with the multi-core system and hides the scheduling characteristics from adversaries. The software-based Earliest Deadline First (EDF) algorithm is also used for schedulability tests and feasibility analysis of hard real-time periodic tasks to maximize the number of tasks scheduled successfully in the multi-core system. SAFAS has been synthesized and simulated on a Xilinx Vivado 2018.2 and implemented on a Spartan-7 FPGA chip. Our experimental results indicate that SAFAS increases the performance of the system by 4.8 times as compared to previous state-of-the-art hardware schedulers while guaranteeing that all critical tasks and their replicas meet their deadlines. [ABSTRACT FROM AUTHOR]

A microgrid is a cluster of several energy sources and interconnected loads which are synchronized to operate either in grid connected or islanded mode. To attain higher efficiency and improved power control the microgrid is integrated with power electronic devices. But various problems arise related to protection among which the major issue to be focused on is islanding detection. Whenever an islanding condition arises the balance between load and generation in the islanded circuit can be violated, thereby leading to abnormal frequencies and voltages. This hazardous state observed in the system can be prevented by early detection of occurrence. In this paper, an active islanding detection with integrated PV system for grid based on Predictive Goertzel algorithm is proposed. The proposed single-phase single stage photovoltaic system injects a small harmonic component of the output of the grid and checks point of common coupling (PCC). The Predictive Goertzel algorithm is a discrete Fourier transform that resolve Non detection Zone (NDZ) and detection time. The highlight of this work is to demonstrate the performance of proposed islanding detection method, a single-stage single-phase grid integrated PV system embraces of 1-Φ full bridge inverter, LCL filter and local load (RLC parallel load) is considered. This algorithm is implemented in MATLAB Simulink environment. From the results obtained, the detection time for real time environment has reduced by 200ms compared to existing algorithm. [ABSTRACT FROM AUTHOR]

Task scheduling is a major challenging issue in parallel and distributed heterogeneous computing systems. The task scheduling problem in a heterogeneous multiprocessor system typically comprises two phases: assigning priority to tasks and mapping tasks to processors. This work considers the task scheduling problem a multi-objective optimization problem to minimize the makespan and maximize the processor utilization. In this paper, the authors have proposed a novel dynamic task scheduling algorithm that is based on an existing metaheuristic algorithm called Black Widow Optimization (BWO) and an existing deep learning method called Deep Recurrent Neural Network (DRNN) to achieve the objective. The scheduling algorithm is called DRNN-BWO (DRNN trained by using BWO). Authors have used the Upward Rank technique to prioritize the tasks and the Priority-based Modules Encoding (PME) technique for mapping tasks to processors. The simulation results of the proposed algorithm are compared with some standard algorithms to find out how they fare against each other in reducing the makespan. The proposed algorithm is also compared with some recently developed metaheuristic algorithms based on some real-life applications. All the simulation results show that the proposed algorithm significantly reduces the makespan and increases processor utilization. [ABSTRACT FROM AUTHOR]

Large biomedical text data represents an important source of information that not only enables researchers to discover in-depth knowledge about biological systems, but also helps healthcare professionals do evidence-based medicine in clinical settings. However, investigating and analyzing these data is often both data-intensive and computation-intensive. In this paper, we investigate how to use MapReduce, a parallel and distributed programming paradigm, to efficiently mine the associations between biomedical concepts extracted from a large set of biomedical articles. First, biomedical concepts were obtained by matching text to Unified Medical Language System (UMLS) Metathesaurus, a biomedical vocabulary and standard database. Then we developed a MapReduce algorithm that could be used to calculate a category of interestingness measures defined on the basis of a 2 × 2 contingency table. This algorithm consists of two MapReduce jobs and takes a stripes approach to reduce the number of intermediate results. Experiments were conducted using Amazon Elastic MapReduce (EMR) with an input of 33,960 articles from TREC (Text REtrieval Conference) 2006 Genomics Track. Performance test indicated that our algorithm had approximately linear scalability and was more efficient than a ‘‘pairs’’ approach in the literature. The physician in our project team evaluated a subset of the association mining results related to drug-disease treatment and found that meaningful association rules ranked high. [ABSTRACT FROM AUTHOR]

Before an application can be actually launched in a many-core system, the first thing that needs to be done is to get the application mapped to a number of tiles (cores). Such online application mapping process may unfortunately lead to a serious resource leak problem, referred as tile fragmentation, that free (uncommitted) tiles from any single contiguous region are just inadequate to accommodate the performance needs of an incoming application, although the total number of free tiles may still exceed what is required to service this application. When applications have to be mapped to noncontiguous tiles due to fragmentation, there will be obvious performance penalty due to increased communication distances. As a result, defragmentation that consolidates fragmented tiles needs to be routinely exercised, and this defragmentation process must not introduce high computation overhead that otherwise can adversely impact the system performance. In this paper, we propose a task migration-based adaptive tile defragmentation algorithm that helps consolidate running applications through online task migration. This algorithm relocates the applications’ tile regions so that a contiguous free tile region is formed and maintained. By doing so, future applications can be mapped to a region with low communication distance. Both the computation overhead and quality of defragmentation result of the proposed algorithm are adaptively set in response to the system workloads. Enabled by its low overhead, the proposed defragmentation algorithm is an effective resource management enhancement to the existing runtime task-to-tile mapping methods, with as much as 3× system throughput improvement observed in some experiments. [ABSTRACT FROM AUTHOR]

Simultaneous Multi-Threading (SMT) processors increase performance by allowing concurrent execution of multiple independent threads with sharing of key datapath components and better utilization of the resources. An SMT processor usually maintains a shared register file to accommodate multiple threads for register renaming. By supporting inter-thread sharing of the physical registers, an SMT system processor can reduce the number of registers that would have been required in multiple superscalar processors while achieving a comparable throughput. However, congested shared resources due to slower threads can easily lead to inefficient usage of the resources and thus an undesirable performance outcome. In this paper, we propose an allocation algorithm at the architectural level for a better utilization of the shared register file. We show that, by limiting the number of the physical register entries each thread is allowed to occupy at any given time, the overall system throughput is enhanced by a substantial margin. An improvement in IPC of up to 44.6% and 32.7% is observed when the proposed technique is applied to a 4-threaded and a 6-threaded SMT system, respectively. Furthermore, a 4-threaded system with a physical register file of 160 entries can deliver a performance comparable to that of a default system with 256 entries, reflecting a resource saving of 37.5%. [ABSTRACT FROM AUTHOR]

This paper aims at presenting a new countermeasure against Side-Channel Analysis (SCA) attacks, whose implementation is based on a hardware-software co-design. The hardware architecture consists of a microprocessor, which executes the algorithm using a false key, and a coprocessor that performs several operations that are necessary to retrieve the original text that was encrypted with the real key. The coprocessor hardly affects the power consumption of the device, so that any classical attack based on such power consumption would reveal a false key. Additionally, as the operations carried out by the coprocessor are performed in parallel with the microprocessor, the execution time devoted for encrypting a specific text is not affected by the proposed countermeasure. In order to verify the correctness of our proposal, the system was implemented on a Virtex 5 FPGA. Different SCA attacks were performed on several functions of AES algorithm. Experimental results show in all cases that the system is effectively protected by revealing a false encryption key. [ABSTRACT FROM AUTHOR]

In the paper an implementation of mobile nodes tracking system based on ZigBee and Wi-Fi wireless networks is presented. On the base of known algorithmic as well as circuit solutions a simple yet universal system, applied in prototype application dedicated for person's localization in museum premises has been developed. Since system utilizes entirely wireless communication, it can be applied in any closed objects. The system has been preliminarily verified in real in-situ environment. [ABSTRACT FROM AUTHOR]

Despite years of railway control and signalling development, modern formal description methods are still not widely used. Lack of standards in the interlocking logic construction method causes the development of the railway control systems to be more and more expensive. Moreover, the microprocessor technology used nowadays reaches its limits regarding signal processing time in decentralised systems. This forces the industry to seek for new solutions. This paper presents an algorithmic approach to interlocking logic development, together with a modern implementation methods using hardware description languages and programmable devices. [ABSTRACT FROM AUTHOR]

Stereo matching is one of the most used algorithms in real-time image processing applications such as positioning systems for mobile robots, three-dimensional building mapping and recognition, detection and three-dimensional reconstruction of objects. In order to improve the performance, stereo matching algorithms often have been implemented in dedicated hardware such as FPGA or GPU devices. In this paper an FPGA stereo matching unit based on fuzzy logic is described. The proposed algorithm consists of three stages. First, three similarity parameters inherent to each pixel contained in the input stereo pair are computed. Then, the similarity parameters are sent to a fuzzy inference system which determines a fuzzy-similarity value. Finally, the disparity value is defined as the index which maximizes the fuzzy-similarity values (zero up to d max ). Dense disparity maps are computed at a rate of 76 frames per second for input stereo pairs of 1280 × 1024 pixel resolution and a maximum expected disparity equal to 15. The developed FPGA architecture provides reduction of the hardware resource demand compared to other FPGA-based stereo matching algorithms: near to 72.35% for logic units and near to 32.24% for bits of memory. In addition, the developed FPGA architecture increases the processing speed: near to 34.90% pixels per second and outperforms the accuracy of most of real-time stereo matching algorithms in the state of the art. [ABSTRACT FROM AUTHOR]

Oriented FAST and Rotated BRIEF (ORB) is becoming the method of choice in real-time feature matching applications by offering performances comparable to other state-of-the-art descriptors at a fraction of the runtime and memory requirements. These characteristics have prompted multiple researchers to propose FPGA-based accelerators that allow for a significant increase in throughput compared to general-purpose processors. This increase is, however, achieved at the expense of the descriptor's robustness as several approximations are necessary to map the algorithm efficiently into hardware which negatively affects its invariance. In this paper, we introduce an FPGA architecture capable of extracting ORB descriptors at high throughput with minimal impact to their invariance. Rotation of sample point coordinates is bypassed entirely, and methods for the accurate computation of the moments and descriptor generation in a single clock cycle are described. Moreover, a feature matching algorithm based on the cross-check criterion is proposed and implemented in hardware. The architecture achieved a throughput of 94 MPix/s using a 100 MHz clock while producing an almost identical performance compared to the reference implementation. • An FPGA-based accelerator of the ORB descriptor is proposed. • Methods for the accurate computation of the patch moments are described. • Rotation of sample point coordinates is bypassed. • The descriptor is computed in a single clock cycle. • Feature matching using the cross-check criterion has been implemented in hardware. [ABSTRACT FROM AUTHOR]