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In this paper, the challenges of dense integration, low power, low-cost, low-noise and high spurious free dynamic range (SFDR) required by the RF front-end (RFE) circuits for low-rate wireless personal area networks are addressed. The proposed RF down-converter circuit utilizes a low-noise transconductance amplifier stage to improve the noise performance of the highly noisy switching stage of the down-converter. The nonlinearity of the low-noise stage is compensated by employing post-distortion based harmonic cancellation for dynamic range improvement of the RF front-end circuit. The proposed RFE is designed and realised in UMC 180 nm CMOS process technology. The post-layout characterization of the circuit shows an third-order intercept point with reference to the input (IIP3) of 11.83 dBm, double-sideband noise figure of 5.9 dB, conversion gain of 17.87 dB and offers a SFDR of 81.88 dB while consuming 5 mA current from 1.8 V. The proposed circuit consumes an area of 0.1 mm2. The proposed RF down-converter boasts a 17 dB improvement in SFDR over the recently proposed RFE in the literature. The proposed RFE is also correlated with the other existing state-of-art RFE circuits recorded in the literature for Zigbee applications. [ABSTRACT FROM AUTHOR]

The frequency bands below 3 GHz are occupied by various wireless applications. The overcrowding of many applications in these bands is the primary source of distortion in the wireless system. To combat distortion in the system, the radio frequency (RF) blocks must satisfy the linearity requirements of the application. Hence, in this paper, a high linear wideband low noise amplifier (LNA) stage is proposed for RF front-end. The LNA uses the combination of common-gate (CG) and common-source (CS) stages for cancelling the noise and distortion of the input matching CG stage. The CS stage exploits complementary derivative superposition (CDS) for linearity improvement, and cross-coupled local feedback network is employed for noise cancellation at the output. The LNA stage is designed using UMC 180 nm CMOS process technology and post-layout characterizations are carried out using Cadence SpectreRF circuit simulator. Also, the process corner, voltage, and temperature (PVT) variation analysis and Monte-Carlo simulations for mismatch analysis are carried out to verify the reliability of the LNA. The designed LNA has an input referred third-order intercept point (IIP3) of 8.85 dBm. The proposed LNA has a maximum gain of 23.96 dB and minimum noise figure (NF) of 1.4 dB with a total current consumption of 3.1 mA from a 1.8 V supply. [ABSTRACT FROM AUTHOR]

In the literature, surfing technique has been proposed for differential on-chip wave-pipelined serial interconnects with uniform repeaters (UR) and non-uniform repeaters to increase the data transfer rate for unidirectional schemes. In this paper, a novel bidirectional data transfer through the differential wave-pipelined serial interconnects with surfing for UR is proposed. A new circuit called 'Bidirectional surfing inverter pair' is proposed for differential wave-pipelined serial interconnects. The method of logical effort is used for the design of surfing circuits. To evaluate the efficiency of these techniques, 40 mm metal 4 interconnects using the proposed surfing techniques are implemented along with transmitter, receiver and delay locked loop in UMC 180 nm technology and their performances are studied through post layout simulations. The proposed bidirectional differential surfing scheme has a maximum data transfer rate of 2 Gb/s and has allowable jitter of 52 ps on both directions through the same interconnects. [ABSTRACT FROM AUTHOR]