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In search for non-toxic thermoelectric materials that are stable in air at elevated temperatures, zinc oxide has been shown to be one of only few efficient n-type oxidic materials. Our bottom-up approach starts with very small (-4 Wm-1K-2 were measured at temperatures higher than 600 °C.

Flash-lamp annealing (FLA) has been investigated for the crystallization of a 60 nm amorphous silicon (a-Si) layer deposited by PECVD on display glass. Input factors to the FLA system included lamp intensity and pulse duration. Conditions required for crystallization included use of a 100 nm SiO2capping layer, and substrate heating resulting in a surface temperature ∼ 460 °C. An irradiance threshold of ∼ 20 kW/cm2was established, with successful crystallization achieved at a radiant exposure of 5 J/cm2, as verified using variable angle spectroscopic ellipsometry (VASE) and Raman spectroscopy. Nickel-enhanced crystallization (NEC) using FLA was also investigated, with results suggesting an increase in crystalline volume. Different combinations of furnace annealing and FLA were studied for crystallization and activation of samples implanted with boron and phosphorus. Boron activation demonstrated a favorable response to FLA, achieving a resistivity ρ < 0.01 Ω•cm. Phosphorus activation by FLA resulted in a resistivity ρ ∼ 0.03 Ω•cm.

This work investigates scanning laser annealing used for ultra-shallow junction (USJ) activation. We investigate the laser system via simulation to determine the peak temperature achieved in the active area during processing. We employed the Sentaurus TCAD software by Synopsys to perform a 2D simulation of a laser scans across the active area of the device, solving the heat equation in both time and space. An absorber layer is deposited on the wafer surface to enhance the absorption of incident energy and reduce SOI reflectivity. An effective absorption coefficient of α=8000cm-1 was calculated for the absorber layer, calibrated with the experimental laser intensity. This absorption coefficient correctly predicts the silicon temperature as a function of power with any arbitrarily defined scan speed. To investigate the role of dopant activation, an SOI wafer was implanted with arsenic 25 keV, dose 3e15 /1.5e15 cm-2 and laser annealed in areas of target temperatures ranging from 850-1300°C. The sheet resistance was measured using 4-point probe showing sheet resistance improvement with increasing laser temperature. The extracted temperature cycle from the 2D heat simulation was used as an equivalent millisecond RTA in a full 3D process simulation to study dopant distribution and activation using Sentaurus Process Kinetic Monte Carlo (KMC), considering the effect of dopants, dopant clusters, and point defects. The results of this simulation demonstrate deactivation of arsenic above 1050°C, which is inconsistent with Hall measurements that suggest increasing laser temperature will increase mobility and activation. The results are analyzed versus the expected trends and suggest future improvements needed to the KMC model or the laser temperature profiles in order to describe activation kinetics in millisecond anneals within SOI.

Controlled incorporation of dopants into semiconductors nanowires is a critical step in tailoring their physical properties and hence for their utilization in future nano electronic devices. Recently, several studies addressing this issue revealed that dopant are inhomogeneously distributed in NWs grown by the popular CVD-VLS growth technique. The majority of those studies employed indirect characterization techniques which are sensitive to the active dopants only. In order to deepen our understanding of the incorporation mechanism a direct observation of the dopant chemical concentrations is required. In addition, the comparison between direct and indirect observations can shed some light on the dopant activation mechanisms in VLS grown NWs. In this study nanoprobe scanning Auger microscopy was employed to extract the longitudinal dopant distribution along P doped SiNWs. The effect of growth conditions and post-growth annealing on this distribution was studied and compared to previous studies which used indirect measurement techniques. In addition, dopant modulated segmented NWs were studied in order to distinguish the contribution of different mechanisms to the incorporation of dopants into VLS grown NWs.

The effect of the rapid thermal annealing (RTA) and hydrogenation step on the electronic properties of the n+ and p+ solid phase crystallized (SPC) poly-crystalline silicon (poly-Si) thin films was investigated using Hall effect measurements and four-point-probe measurements. Both the RTA and hydrogenation step were found to affect the electronic properties of doped poly-Si thin films. The RTA step was found to have the largest impact on the dopant activation and majority carrier mobility of the p+ SPC poly-Si thin films. A very high Hall mobility of 71 cm2/Vs for n+ poly-Si and 35 cm2/Vs for p+ poly-Si at the carrier concentration of 2×1019 cm-3 and 4.5×1019 cm-3, respectively, were obtained.

Variable frequency microwaves (VFM) and rapid thermal annealing (RTA) were used to activate ion implanted dopants and re-grow implant-damaged silicon. Four-point-probe measurements were used to determine the extent of dopant activation and revealed comparable resistivities for 30 seconds of RTA annealing at 900 °C and 6-9 minutes of VFM annealing at 540 °C. Ion channeling analysis spectra revealed that microwave heating removes the Si damage that results from arsenic ion implantation to an extent comparable to RTA. Cross-section transmission electron microscopy demonstrates that the silicon lattice regains nearly all of its crystallinity after microwave processing of arsenic implanted silicon. Secondary ion mass spectroscopy reveals limited diffusion of dopants in VFM processed samples when compared to rapid thermal annealing. Our results establish that VFM is an effective means of low-temperature dopant activation in ion-implanted Si.

The electrical characteristics of high quality single crystal boron-doped diamond are studied. Samples are synthesized in a high power-density microwave plasma-assisted chemical vapor deposition (CVD) reactor at pressures of 130-160 Torr. The boron-doped diamond films are grown using diborane in the feedgas at concentrations of 1 to 50 ppm. The boron acceptor concentration is investigated using infrared absorption and a four point probe is used to study the conductivity. The temperature dependent conductivity is analyzed to determine the boron dopant activation energy.

The role of the dopant activation on the segregation efficiency during the formation of platinum silicide (PtSi) is investigated in this paper. Using an implant before silicidation technique, we first demonstrate an important Schottky Barrier Height (SBH) modulation for As and B segregation. In the case of As, we highlight that an activation of the dopants before the silcidation does not impact the SBH modulation. On the contrary, an important impact of the dopant crystalline position is evidenced for Boron. Also, a comparison of conventional implant versus a PLAsma Doping (PLAD) highlights the suitability of the latter implantation tool for the SBH modulation. Those results are interpreted on the basis of SIMS depth profiling.

The control and understanding of the incorporation of nitrogen during SiC PVT continues to play an important role in SiC crystal growth. Nitrogen acts both as a dopant and an impurity depending on the growth conditions and desired resistivity. Epitaxial growth by CVD provides some insight into N incorporation in terms of the face effects, temperature, and impact of the chemical species in terms of the C/Si ratio. This paper will present experimental results showing trends regarding nitrogen incorporation during SiC PVT. Various crystal growth processes operated under constant nitrogen partial pressures were found to produce wide ranges of SiC resistivity. These effects will be analyzed in light of the process impact on gas phase elemental composition (1), crystal stress (2), dopant activation (3) and crystal defectivity (4). The goal of this paper is to provide additional insights regarding nitrogen incorporation during SiC PVT, and in turn drive towards a more holistic approach to control the resistivity of 4H n+ SiC material, based on the understanding established from SiC epitaxy technology.

The use of millisecond annealing to meet ultra-shallow junction requirements for sub-45nm CMOS technologies is imperative. In this study, the effect of flash anneal parameters is presented. Reduced dopant diffusion and lower sheet resistance Rs is achieved for intermediate temperature Tint = 700°C (vs. 800°C). Significantly lower Rs is achieved with peak temperature Tpeak = 1300°C (vs. 1250°C). Multiple shots provide for lower Rs, albeit at the expense of increased dopant diffusion. Based on a simple quantitative model, an optimal flash anneal can achieve 82% dopant activation efficiency.

The impact of low temperature plasma resist strip on doped silicon surface and microelectronic device performance is investigated using different chemical gas mixtures. In this investigation, different plasma treatments where applied on non-structured and structured silicon on insulator (SOI) wafers post ultra shallow surface implants .The main surface impacts dopant bleaching and oxide loss in conjunction with plasma enhanced re-oxidation are analyzed by time of flight secondary ion mass spectrometry (TOF-SIMS) and electrical measurements of microelectronic test devices. As the result, a long range plasma radiation induced dopant activation and deactivation is separated as the main effect from surface oxide loss and re-oxidation processes. This implies further optimization of plasma resist strip processes for device improvements.

Germanium has regained attention in the semiconductor industry for MOSFET application because of the higher mobility of carriers – two times higher mobility for electrons and four times for holes – as compared to silicon. In the opposite of the Silicon, the major issue with Germanium is to limit the n-dopant diffusion. Usual n-dopants (Phosphorus and Arsenic for example) are not electrically activated at an acceptable level without a large diffusion of the doping profile and a substantial dose loss. In this work, we have studied the influence of low energy and dose implant (15KeV to 40KeV @ 8E13 to 1E15at.cm−2) and low temperature anneal (515°C to 600°C) on diffusion, exodiffusion and activation of the phosphorus dopant into Germanium. The annealing steps were made in RTP furnace, the chemical profile and electrically active profiles were extracted by using Secondary-Ion-Mass Spectroscopy (SIMS) and sheet resistance measurement (Rs). To investigate the implantation-induced defects in depth, cross-sectional micrographs were made by using Transmission Electron Microscopy (TEM). Experimental results show that we achieved an efficient activation level by tuning both dose implant and anneal temperature, limiting the exodiffusion with pratically no diffusion of the dopant. We also show that very abrupt profile can be achieved with appropriate implant and thermal annealing conditions. To limit the leakage current in devices, we suppose we have to limit the defects generated during the implantation. Specially for dopant activation temperature anneal below 550°C, we have shown and observed by cross-sectional micrograph that the defects are totally removed by addition of a pre step of annealing at 400°C.

The behavior of point defects within silicon can be changed significantly by controlling the chemical state at the surface. In ultrashallow junction applications for integrated circuits, such effects can be exploited to reduce transient enhanced diffusion, increase dopant activation, and reduce end-of-range damage.

Laser annealed junctions and advanced ultra shallow junctions are studied in both atomistic modeling and experiments. SIMS and sheet resistance measurement for spike-RTA + Laser annealing show that additional laser annealing after spike-RTA (“+Laser”) improve the dopant activation level without increasing in junction depth. “+Laser” effect become effective in the combination of low spike-RTA temperature and high laser temperature. This effect is significant for As doped layer. Spike-RTA based junction has a limitation in viewpoint of Rs-Xj trade-off. Laser-only annealing is promising candidate to overcome this limitation. Boron diffusion with laser-only annealing is investigated. As atomistic kinetic Monte Carlo modeling show that BnImcomplexes and End-of-Range (EOR) defects are formed during sub-millisecond annealing time range. Impact of F co-implant on Boron diffusion and EOR defect evolution during sub-millisecond annealing are also investigated.

We report continuous-wave (CW) infrared-semiconductor laser annealing of silicon implanted with boron atoms with assistance of diamond-like carbon (DLC) films as optical absorption layer in order to form shallow junctions. BF2 ions were implanted at 10 keV at doses of 1.5×1015 cm−2 thorough an 8-nm thick SiO2 layer. The effective boron dose implanted into silicon was 7.5c1015 cm−2 a half of the implantation dose. The initial boron distribution had a peak concentration of 6×1020 cm−3 at the silicon surface and a concentration of 1×1019 cm−3 at a depth of 27 nm. The samples were coated with 200-nm-thick DLC films. The samples were annealed by irradiation with a 940 nm continuous wave laser at 80 kW/cm2 with a beam diameter of 180 μm for 2.6 ms. Heat flow analysis estimated that the sample surface was heated to 1350°C for 1.5 ms by laser annealing. Laser annealing markedly reduced the sheet resistance to 531 Ω/sq. Boron atoms were almost completely activated with a carrier density close to the effective boron dose of 7.5×1014 cm−2. The in-depth profile of boron concentration hardly changed within 3 nm for laser annealing for 2.6 ms. The intermediate SiO2 layer effectively blocked carbon incorporation to a level below 1017 cm−3. These results show that the present laser annealing method is suitable to form shallow junction of a high dopant activation ratio. We will report low energy implantation of boron-cluster ions followed by the present infrared-semiconductor laser annealing in order to form a shallow junction with a depth less than 15 nm.

Microwave heating is used to activate solid phase epitaxial re-growth of amorphous silicon layers on single crystal silicon substrates. Layers of single crystal silicon were made amorphous through ion implantation with varying doses of boron or arsenic. Microwave processing occurred inside a 2.45 GHz, 1300 W cavity applicator microwave system for time-durations of 1-120 minutes. Sample temperatures were monitored using optical pyrometery. Rutherford backscattering spectrometry, and cross-sectional transmission electron microscopy were used to monitor crystalline quality in as-implanted and annealed samples. Sheet resistance readings show dopant activation occurring in both boron and arsenic implanted samples. In samples with large doses of arsenic, the defects resulting from vacancies and/or micro cluster precipitates are seen in transmission electron micrographs. Materials properties are used to explain microwave heating of silicon and demonstrate that the damage created in the implantation process serves to enhance microwave absorption.

The modeling of atomistic processes in semiconductors based on the density functional theory is outlined. The role of intrinsic defects in the self and dopant diffusion, as well as in the dopant activation is investigated for the case of silicon carbide. A hierarchy of annealing mechanisms for vacancies and interstitials is proposed. The identification of the microscopic origin of experimental defect centers by calculated defect signatures establishes a link between theoretical modeling and experiments.

Boron diffusion and defect evolution during sub-millisecond (ms) laser annealing with partial SPER are investigated using secondary ion mass spectrometry and transmission electron microscopy. Boron diffusivity enhancement in amorphous-Si is observed during partial SPER at 550 °C. It is shown that boron diffusion during the laser annealing process is a 2-step diffusion (SPER + Laser). The depth of the amorphous layer affects the dopant activation behavior. During sub-ms laser annealing, end-of-range defects are formed and show an evolution behavior. {311} defects cannot completely transfer to dislocation loops after 1300 °C laser annealing. It is considered that the thermal budget of sub-ms laser is too small for full defect evolution. Atomistic diffusion modeling using a kinetic Monte Carlo method can explain the defect behavior during laser annealing.

The challenge of achieving maximal dopant activation with minimal diffusion has re-awakened interest in millisecond-duration annealing processes, almost two decades after the initial research in this field. Millisecond annealing with pulsed flash-lamps or scanned energy beams can create very shallow and abrupt junctions with high concentrations of electrically active carriers, but solutions for volume manufacturing must also meet formidable process control requirements and economic metrics. The repeatability and uniformity of the temperature cycle is the key for viable manufacturing technology, and the lessons from the development of commercial rapid thermal processing (RTP) tools are especially relevant. Advances in the process capability require a fuller understanding of the trade-off between dopant activation, defect annealing. diffusion and deactivation phenomena. There is a strong need for a significant expansion of materials science research into the fundamental physical processes that occur at the short time scales and high temperatures provided by millisecond annealing.

In this overview we examine how advanced continuum and atomistic modeling can help to understand and resolve process and device design issues for the 65 nm technology generation and beyond. The following implantation-related issues are reviewed: wafer temperature for different types of implant equipment and its impact on defect formation and amorphization, ion scattering off the photoresist mask and its impact on threshold voltage variation, dual rotation halo implant instead of the conventional quad rotation halo implant, and engineering of the source/drain junction overlap for diffusionless annealing by using tilted implants. The following annealing-related issues are also considered: limitations of spike anneal; benefits of cocktail junctions, heat transfer mechanisms for spike and millisecond annealing, and implant damage evolution for different thermal budgets. Taken together, implant, annealing, and layout conditions are shown to explain observed threshold voltage and transistor performance variations. In addition, the effects of transistor geometry on dopant diffusion, activation, and defect formation are shown for several generations of bulk and FDSOI MOSFETs.

The ability to activate greater amounts of dopants is a significant challenge for the realization of shallow junctions in device scaling for Si CMOS technology. Dopant activation is difficult to achieve in shallow junctions due to higher concentrations of dopants and possible formation of dopant clusters. The high temperatures currently used to activate dopants result in increased junction depth and process integration issues with high-k dielectrics. However, lowering the annealing temperature results in lesser dopant activation and problems with transient enhanced diffusion. Our previous work reported on the enhancement of activation in boron implanted at a dose of 5E14/cm2 and annealed at temperatures of 450 °C and below, by the incorporation of atomic hydrogen introduced by exposing the substrate to a hydrogen plasma at 250 °C. In this work, further experiments have been carried out to get a better understanding of the mechanisms responsible for boron activation enhancement. Hydrogen-related activation was studied in boron, phosphorus and antimony implanted samples. The experimental results shed new light on the interactions among atomic hydrogen, point defects and dopants.

High levels of electrical activation of both p- and n-type dopants are realized by pre-amorphization implantation (PAI) in bulk germanium wafers and germanium-on-insulator (GOI) substrates. In bulk germanium, p-type dopant yields an electrical activated concentration of 1.5×1020 /cm3 after a 400°C rapid thermal annealing (RTA), which is one order higher than obtained for samples without PAI. N-type dopants also show comparable improvement as 1×1020 /cm3 after 600°C RTA. Both results are the highest ever being reported and are sufficient for advanced CMOS applications. PAI was also employed in dopant activation for GOI substrates. Carrier concentrations of 6×1020 /cm3 and 5×1019 /cm3 were observed for p- and n-type dopants respectively after identical RTA conditions as for bulk germanium counterparts. Hydrogen incorporated in GOI wafers which were prepared by Smart-Cut™ approach may be responsible for the discrepancy of activated concentrations between bulk germanium and GOI. Nevertheless, PAI shows the promise of dopant activation in germanium and can be readily adopted in current CMOS processes.

Doping of polysilicon (poly-Si) films was performed at a low temperature (4 Ω/sq., which were considered to be sufficient to form good source-drain contacts. Also, a sheet resistance value that is as low as 300 Ω/sq. was demonstrated. It was found that the laser energy used for dopant activation was the major parameter to control the sheet resistance of the poly-Si films. The lowest attainable sheet resistance was not affected much by the ion dose, as long as the initial dose is higher than 1015 cm−2. The plasma immersion method was shown to be a good alternative to the ion shower, as the doping could be performed in a relatively short time without causing a structural damage to the poly-Si film.

Boron and phosphorus were implanted into (100) Ge with energies ranging from 20-320 keV and doses of 5×1013 to 5×1016 cm−2. The as-implanted and annealed dopant profiles were examined using secondary ion mass spectrometry (SIMS) and spreading resistance profiling (SRP). The first four moments were extracted from the as-implanted profile for modeling with Pearson distributions over the entire energy range. The samples were annealed at 400, 600, or 800°C in nitrogen ambient. The dopant activation and diffusion were also examined and it was found that p-type sheet resistances immediately after boron implantation as low as 18 ohms/sq could be obtained without subsequent annealing.

One of the main materials challenges of the 130 nm silicon technology node was the need to find a processing solution to the anomalous diffusion behavior of ion-implanted dopants known from three decades of research. Reduction of implantation energy no longer proved sufficient when trying to reduce source/drain extension junction depth, increase abruptness, and limit sheet resistance. Spike-annealing, a new process in which ion implanted silicon could be heated rapidly to temperatures required for dopant activation and then cooled down without dwelling at temperature, adequately addressed the scaling requirements of this node. The resulting junctions achieved high dopant concentration values very close to the surface while limiting junction depth. However, this increased the propensity for dopant migration to overlying layers associated with the source/drain spacer. Loss of device performance due to this and other phenomena became a strong motivating factor for further materials research in order to sustain progress through the 130 nm and 90 nm nodes. Complex interactions between various layers have been understood and the resulting developments in spacer materials have enabled high performance devices. The requirements of the 65 and 45 nm nodes stretch spike-annealing to its limit and newer Ultra-High Temperature anneals must be considered.

The creation of ultra-shallow junction for CMOS devices at the sub-100 nm node is driving significant efforts in developing thermal processing to give rise to high dopant activation in combination with limited diffusion. Flash-assist Rapid Thermal Annealing™ (fRTP™) is a promising new annealing technique, which involves the heating of the bulk of the wafer to an intermediate temperature using rather conventional spike RTP, followed by a short and intense pulse of light localized on the implanted wafer surface.In this work, we have systematically investigated the junction formation of different implants under fRTP anneals in terms of profile and devices. Co-implanted Ge and F species provide more box-like profiles with improved activation. Although leakage currents are higher for fRTP-annealed junctions than for spike-annealed junctions, appropriate fRTP process parameters and correct process conditions provide a critical tool to control and reduce the leakage current of co-implanted fRTP junctions to acceptable levels. Proper implant and anneal are requested for minimizing pattern effect and improving device performance.

In the fabrication of thin film transistors (TFTs), little attention has been paid to the polycrystalline silicon thin films prepared at low temperatures where the glass substrates are adopted so far. Since the film quality is not sufficient to achieve high mobility, e.g., over 50 cm2/Vs in spite of high benefit in their industrial fabrication. We have fabricated bottom gate TFTs with poly-Si and poly- Si1-xGex thin films deposited at 450°C by newly developed low-temperature LPCVD technique and characterized electrical characteristics of the TFTs: disilane and a small amount of either germanium tetrafluoride or fluorine were used as material gases and helium as carrier gas. Thermal annealing for dopant activation and atomic hydrogen treatment for defect passivation were carried out. We found that the defect elimination process is important for improving TFT performance significantly. Finally the mobility of p-channel and n-channel TFTs have attained 36.3-54.4 cm2/Vs and 57 cm2/Vs, respectively.

The characteristics of dopant activation by sequential lateral solidification in poly-Si films is investigated using sheet resistance measurement and Raman measurement. Sheet resistance of n+ and p+ doped poly-Si films decreases exponentially as the laser energy increases. The minimum sheet resistance of n+ doped poly-Si films is 150 Ω/□ which is near to that of rapid thermal annealing (RTA) while the minimum sheet resistance of p+ doped poly-Si films is 180 Ω/□ which is less than a half to that of RTA. The sheet resistance of n+ and p+ doped poly-Si increases as the laser energy increases when the laser energy is above 573 mJ/cm2 at which the nucleation occurs. Raman signal of n+ doped poly-Si films shows single peak at 515 cm-1 with all laser energy and has maximum intensity at 566 mJ/cm2 laser energy. Raman signal of p+ doped poly-Si films shows single peak below 413 mJ/cm2 laser energy and double peak above 444 mJ/cm2 laser energy where the fully melting of p+ doped poly-Si film occurs.

One of the major advantages of multiple-pulses Laser Thermal Annealing (LTA) with moderate energy fluence is that good dopant activation can be achieved without further increases in junction depth by successive pulses. It is demonstrated that when the laser fluence is adjusted to a value that can melt the preamorphization implantation (PAI) layer but not the underlying silicon substrate, PAI layer depths control the junction depths. Hence, it is desirable to operate LTA in this regime since this allows for a tighter process control as opposed to when the junction depth is controlled solely by the laser fluence. High Resolution Transmission Electron Microscopy (HR-TEM) micrographs show that the degree of damage repair depends on the amorphous layer thickness as well as the number of pulses. Our study allows for the evaluation of the maximum allowable PAI depth for a given number of pulses in order to fully remove the damage caused by the PAI.

In this paper, we investigate the effect of post-implant annealing on the optical and electrical properties of Si-implanted GaN films. Results from several measurement techniques including room temperature photoluminescence (PL), micro-Raman scattering, high resolution X-ray diffraction (HRXRD) and Hall measurement are correlated to study the behavior of damage removal, dopant activation, crystalline quality and residual stress, etc. The Hall measurement demonstrates that reasonable activation percentage is achieved though there is only partial recovery of the PL intensity. Raman scattering shows the decrease of stress within the implanted films after thermal annealing. The carrier concentration increases monotonically with increasing annealing temperature up to 1100°C, which is in agreement with linewidth broadening of near band edge in PL spectrum. Moreover, systematic measurements implies that the implantation induced defects, especially point defects, which could play significant role in either the optical or electrical properties of films, cannot be completely annealed out at 1100°C.

Low temperature shallow junction formation is an attractive activation technique for 70nm technology node and beyond as it can easily be integrated into device structures that are formed using disposable spacer (reverse source drain extension formation) or low power CMOS devices using high-k/metal gate stack structures. Therefore, this paper will first review the shallow junction requirements as stated in the 2001 ITRS (international technology roadmap for semiconductors) and it's interpretation to ion implantation shallow junction formation for various dopant activation and annealing techniques. First high temperature (>1000°C) RTA spike, flash or sub-melt laser annealing techniques with oxide or oxynitride/polysilicon electrode gate stack structures will be discussed and its limitations to >8E19/cm3 boron electrically active dopant level due to boron solid solubility limit in silicon satisfying only the 100nm technology node requirement (2003). Next, higher temperature laser melt annealing (1200°C to 1400°C) will be discussed and it's applicability beyond 70nm node technology (2006) to 25nm node (2016) where boron solid solubility limit is up to 5E20/cm3. However, if high-k (HfO) dielectric/metal electrode gate stack structures are to be used starting at sub-100nm node in 2005 for low power CMOS then low temperature (>700°C) annealing must be used for shallow junction formation to prevent recrystallization and dielectric constant degradation. Using low temperature SPE (solid phase epitaxial regrowth) annealing techniques in the 550°C to 750°C for short anneal times of >5mins., shallow & abrupt junctions 8.0nm deep, >2.0nm/decade with up to 2.5E20/cm3 boron electrical active dopant level can be achieved satisfying the 25nm technology node (2016) requirements.

Using a hot-wall rapid thermal system which permits single-wafer processing, thin gate dielectrics consisting of silicon nitride films were fabricated by low pressure chemical vapor deposition (LPCVD). Nitride layers deposited from dichlorosilane (DCS) and ammonia exhibited greatly reduced electrical leakage current compared to silane-based nitride films which are conventionally used in lamp-based single-wafer rapid thermal technology. After a postdeposition anneal, the DCS-based gate dielectric films showed better diffusion barrier properties against boron penetration than silane-based gate dielectrics at a dopant activation temperature of 1000°C.

Electromagnetic heating provides a novel alternative to “illumination-based” rapid thermal processing techniques. Exposure to radiation, in the RF and microwave frequency regimes, rapidly heats silicon (∼125°C/sec) to temperatures in excess of 1000°C without the use of a susceptor. These ramp rates make this technology suitable for the activation of shallow implanted dopants, and satisfaction of the 100 nm technology node has been achieved. Furthermore, the presence of high frequency electric fields creates ponderomotive forces that may alter the kinetics of dopant activation and diffusion. These additional driving forces could, once fully understood, lead to an enhanced activation mechanism that activates sufficient dopants to satisfy the 70 nm technology node at temperatures less than 1000°C.

One alternative to conventional rapid thermal annealing (RTA) of implants for ultra-shallow junction formation is that of laser annealing. Laser thermal processing (LTP) incorporates an excimer pulsed laser capable of melting the near surface region of the silicon (Si) substrate. The melt depth is dependent upon the energy density supplied by the irradiation source and the melting temperature of the substrate surface. A process window associated with this technique is able to produce similar junction depths over a range of energy densities due to the melting temperature depression established with pre-amorphization of the substrate surface prior to dopant incorporation. The process window of germanium (Ge) preamorphized, boron (B) doped Si was investigated. 200 mm (100) n-type Si wafers were preamorphized via 18 keV Ge+ implantation to 1x1015/cm2 and subsequently implanted with 1 keV B+ to doses of 1x1015/cm2, 3x1015/cm2, 6x1015/cm2, and 9x1015/cm2. The wafers were laser annealed from 0.50 J/cm2 to 0.88 J/cm2 using a 308 nm XeCl excimer irradiation source. Transmission electron microscopy (TEM) was used to determine the process window for each implant condition, and correlations between process window translation and impurity concentration were made. Four-point probe quantified dopant activation and subsequent deactivation upon post-LTP furnace annealing.

Scaling of devices requires not only shallow junctions but also high levels of dopant activation. For boron as the main p-type dopant, the latter requirement is especially problematic since small clusters of boron atoms and self-interstitials, known also as boron-interstitial clusters (BICs), were found to deactivate and immobilize large fractions of the implanted atoms during post-implantation annealing. In this article, the properties of BICs are reviewed and their influence on semiconductor processes are highlighted.

Hafnium-based dielectrics are under wide consideration for high-K gate dielectric applications. Since the gate electrode typically used in CMOS integration consists of polysilicon with n- or p-type dopants, compatibility of the HfO2layer with the polySi deposition and dopant activation steps is critical. Capacitors were fabricated with HfO2films deposited by ALD and MOCVD, and using polysilicon gate electrodes deposited by CVD processes. These devices showed leakage failures with yields that were observed to depend on the area, dielectric thickness and annealing conditions during the process. Investigation of the root cause of these leakage failures suggested that the leakage failures may be caused by a defect-related mechanism. The implication of this is that the leakage occurs at localized ‘defect’ sites rather than broadly through the HfO2layer. Emission microscopy analysis and physical characterization of the HfO2film were used to corroborate the proposed model. Defect density was observed to be strongly dependent on the processing of the dielectric film. In order to make Hf-based dielectric stacks compatible with polysilicon for conventional CMOS transistor integration with acceptable yield, further postdeposition treatment may be necessary to eliminate or cure the defects.

Dopants diffusion, activation and pile-up due to rapid thermal annealing of implanted Al and B in a thin (∼200Å) Si cap layer on top of Si1-x-yGexCy layer were studied. Experimental results show that both the lattice strain and differential diffusion flux can cause atomic pile-up at the interface and the evidences of those effects were shown independently to each other in this paper. In addition, the pile-up can be extended from the interface to the surface by incorporating C in the underlying layer where B diffusion is much less than in the cap Si. Material analysis shows that both B atomic and activated concentrations in the Si cap layer are increased by 50 %, which suggests that the dopant activation can be increased and junction depth can be decreased at the same time using the inserted Si1-x-yGexCy diffusion blocking layer.

Recently, selectively deposited SiGeB alloys have been proposed to form ultra-shallow source/drain junctions for 35-70 nm CMOS. The technology provides super-abrupt junctions with above equilibrium dopant activation at temperatures lower than 800°C. In addition to their low resistivities, the lower bandgap of SiGeB provides the potential advantage of reducing the Schottky barrier height and therefore, the junction contact resistance. This is a critical concern for future CMOS technology nodes since the contact resistance will dominate the MOSFET series resistance unless new technologies yielding contact resistivities near 10−8 ω−cm2 are developed. This paper examines the solid phase reactions of Ni and Pt with SiGeB alloys in order to form self-aligned low resistivity contacts. The results show that both Ni and Pt can form germanosilicides with low sheet resistances. Furthermore, both metals can form self-aligned contacts with a contact resistivity near 10−8 ω−cm2.

A simple process sequence for fabrication of low temperature polysilicon (LTPS) TFTs with self-aligned graded LDD structure was demonstrated. The graded LDD structure was self-aligned by side-etch of Al under the photo-resist followed by excimer laser irradiation for dopant activation and laterally diffusion. The graded LDD polysilicon TFTs were suitable for high-speed operation and active matrix switches applications because they possessed low-leakage-current characteristic without sacrificing driving capability significantly and increasing overlap capacitance. The leakage current of graded LDD polysilicon TFTs at Vd = 5V and Vg = −10V could attain to below 1pA/μm without any hygrogenation process, when proper LDD length and laser activation process were applied. The on/off current ratios of these devices were also above 108. Furthermore, due to graded dopant distribution in LDD regions, the drain electric field could be reduced further, and as a result, graded LDD polysilicon TFTs provided high reliability for high voltage operation.

We investigated the electrical characteristics of the MOSCAP structures with W/WNx/poly Si1−xGex gates stack using C-V and I-V. The low frequency C-V measurements demonstrated that the flat band voltage of the W/WNx /poly Si0.4Ge0.6 stack was lower than that of W/ WNx /poly Si0.2Ge0.8 stack by 0.3V, and showed less gate-poly-depletion-effect than that of W/ WNx /poly- Si0.2Ge0.8 gates due to the increase of dopant activation rate with the increase of Ge content in the poly Si1−xGex films. As Ge content in poly Si1−xGex increased, the leakage current level increased a little due to the increase of direct tunneling and QBD became higher due to the lower boron penetration.

Heavily-doped, ultra-shallow junctions in boron implanted silicon using pulsed laser annealing have been created. Laser energy in the nonmelt regime has been supplied to the silicon surface at a ramp rategreater than 1010°C/sec. This rapid ramp rate will help decrease dopant diffusion while supplying enough energy to the surface to produce dopant activation. High-dose, non-amorphizing 1 keV, 1e15 ions/cm2 boron is used. Four-point probe measurements (FPP) show a drop in sheet resistance withnonmelt laser annealing (NLA) alone. Transmission electron microscopy (TEM) shows the NLA dramatically affects the defect nucleation resulting in fewer defects with post annealing. Hall mobility and secondary ion mass spectroscopy (SIMS) results are also shown.

This paper addresses the optimization of ion implantation and rapid thermal annealing for the fabrication of shallow junctions and the activation of polycrystalline silicon gates in deepsubmicron CMOS transistors. Achieving ultrashallow, low-resistance junctions was studied by combining low-energy B and As implantation with spike annealing. In addition, experiments using B doping marker superlattices were performed to identify the critical physical effects underlying dopant activation and diffusion. The combination of high ramp rates (∼100 °C/s) and ∼1 s cycles at temperatures as high as 1100 °C can be used to improve dopant activation without inducing significant thermal diffusion after TED has completed. MOS capacitors were used to identify the implantation and annealing conditions needed for adequate activation of the gate electrode. In comparison to the conventional recrystallized amorphous Si gates, it was found that fine-grained poly-Si allows for the use of lower processing temperatures or shorter annealing times while improving the gate activation level. The fine-grained crystal structure enhances the de-activation of B dopants in PMOS gates during the thermal treatments following gate activation. Yet, the resulting dopant loss stays within acceptable limits as verified by excellent 0.18 μm device performance. The feasibility of spike annealing and poly-Si gate materials for 100-nm technology was proven by full integration using gate lengths down to 80 nm.

We analyze the requirements that the International Technology Roadmap for Semiconductors (ITRS) implicitly imposes on the two-dimensional source/drain (SD) dopant profile and translate the results into implant parameters (energy, dose, peak concentration). We do this by determining the voltage drop that the SD current develops across the three main (exclusive of the channel) resistive components in the current path: the spreading resistance in the extension region; the metal-semiconductor contact; and the resistance in the link-up region where the SDregion meets the channel. The largest resistance occurs in the link-up region, followed by the resistance of the contact; the extension contribution is the smallest. The extension resistance requirement can be satisfied by ion-implantation for all generations of the ITRS. The link-up region requires very abrupt lateral profiles, not demonstrated so far by ion-implantation. It is found that such resistance cannot be reduced without impacting the intrinsic device behavior. The contact eventually necessitates dopant concentrations in excess of solid solubility and for NMOS in excess of the fundamental limit of dopant activation.

To continue scaling dimensions of transistors, higher dopant concentration levels are needed for ultra-shallow contacts. Therefore studies of dopant activation have been performed in preamorphized silicon wafers with various boron implant conditions to determine the maximum achievable dopant concentrations after Solid Phase Epitaxial Regrowth (SPER) alone. In the first experiment a silicon piece was preamorphized with a 30 keV, 1×1015 cm−2 and 90 keV, 1×1015 cm−2 Si+ implant followed by a 30 keV, 1×1015 cm−2 B+ implant. Solid phase epitaxial regrowth at 500 °C indicates that boron can be activated at low temperatures. Ultra Low Energy (ULE) implants were studied in the second experiment. Silicon wafers were implanted with 2.5 keV, 1×1015 cm−2 Si+ to amorphize and then B+ was implanted at 0.5 keV in the dose range of 1×1015 to 9×1015 cm−2. Samples were annealed in the temperature range of 500 to 650 °C. High concentrations of boron make it difficult to fully regrow amorphous layers and thus yield marginal electrical properties. Much of the boron remains inactive, particularly at the higher dose implants. In both experiments Variable Angle Spectroscopic Ellipsometry (VASE) is used to measure amorphous layer thickness and Hall effect measures active boron dose. For the first experiment, Secondary Ion Mass Spectrometry (SIMS) data compares chemical dose to active dose during the regrowth process. Sheet resistance data is obtained from a four point probe for the ULE implant experiment.

The interaction between boron and silicon interstitials caused by ion implant damage is a physical process which hinders the formation of ultra-shallow, low resistivity junctions. The possibility of mitigating the effective interstitial point defect population via introduction of nonmetallic impurities in ion implanted silicon has been investigated. Amorphization of a n-type Czochralski wafer was achieved using a series of Si+ implants of 40 keV and 150 keV, each at a dose of 1×1015/cm2. The Si+ implants produced a 2800Å deep amorphous layer, which was then implanted with 8 keV 1×1014/cm2 B+. The samples were then implanted with high doses of either carbon, oxygen, sulfur, chlorine, selenium, or bromine. The implant energies of the impurities were chosen such that the damage and ion profiles of the impurity were contained within the amorphous layer. This allowed for the chemical species effect to be studied independent of the implant damage caused by the impurity implant. Post-implantation anneals were performed in a tube furnace at 750° C. Secondary ion mass spectrometry was used to monitor the dopant diffusion after annealing. Hall effect measurements were used to study the dopant activation. Transmission electron microscopy (TEM) was used to study the end-of-range defect evolution. The addition of carbon and chlorine appear to reduce the boron diffusion enhancement compared to the boron control. Carbon and chlorine also appear to prevent boron out-diffusion during annealing compared to the control, which exhibited 20% dose loss following annealing.

Implantation of dopant ions in SiC has evolved according to the assumption that the best electrical results (i.e., carrier concentrations and mobility) are achieved by using the highest possible processing temperature. This includes implantation at > 600°C followed by furnace annealing at temperatures as high as 1750°C. Despite such aggressive and extreme processing, implantation suffers because of poor dopant activation, typically ranging between < 2%–50% with p-type dopants represented in the lower portion of this range and n-types in the upper. Additionally, high-temperature processing can led to several problems including changes in the stoichiometry and topography of the surface, as well as degradation of the electrical properties of devices. A novel approach for increasing activation of implanted dopants in SiC and lowering the activation temperature will be discussed. This approach utilizes the manipulation of the ion-induced damage to enhance activation of implanted dopants. It will be shown that nearly amorphous layers containing a small amount of residual crystallinity can be recrystallized at temperatures below 900°C with little residual damage. It will be shown that recrystallization traps a high fraction of the implanted dopant residing within the amorphous phase (prior to annealing) onto substitutional sites within the SiC lattice.

Defect creation mechanisms during solid phase crystallization (SPC) of Si thin films were investigated with PECVD amorphous precursor samples produced with various deposition temperatures and thicknesses. These precursor films were implanted with dopant and then crystallized to obtain both SPC and dopant activation. The doping efficiency was found to decrease with the tensile stress level as measured by Raman shift. The stress shows a decrease as the precursor deposition temperature and thickness are lowered. Furthermore, a lower level of stress is induced by rapid thermal annealing when the annealing temperature is high enough to soften the glass substrate on which the films were deposited. We show that by control of stress during the SPC step, intragrain defect density can be lowered and electronic quality of the resulting polycrystalline Si films can be improved. Based on these observations, we propose the following tentative model to explain the defect creation: during SPC, tensile stress evolution is considered to result from the volumetric contraction of Si film when it transforms from the amorphous to crystalline phase. This contraction is retarded by the substrate, which imposes a tensile stress on the film. A high level of stress leads to formation of structural defects inside the grains of the resulting polycrystalline material. These defects trap carriers or complex with the dopant reducing doping efficiency.

Experiments have been caried out to form ultra-shallow (Xj 2, Xj ∼ 23 nm, Xjs ∼ 48 A/decade, no Ge end of range damages and good dopant activation at the same time.The sheet resistance ρ − 1 kohm/sq is comparable to shallow BF2 + Ge and is better than the shallow BF 2 alone (ρ ∼ 2.38 kΩ/sq) or the shallow BF2 + Si implants (ρ ∼ 1.5 kohm/sq). Tests with device leakage test structures show that there is no additional junction leakage introduced by the Si getter layer.

Boron was implanted into n-type Si at energies from 500 eV to 1 keV and doses near 1 E14 cm-2and 1E51 cm−2. Electrical activation was achieved by rapid thermal annealing (RTA) in nominally pure N−2and 0.1% 02 with the fastest available heating rates of up to 150 °C/s, cooling rates up to 80 °C/s, and included “spike” anneals with minimum dwell time at peak temperature. Measurements of sheet resistance, Hall coefficient, and secondary ion mass spectroscopy profiling were used to determine dopant activation and diffusion. Surface oxidation was studied by film thickness ellipsometry. Analyses of electrical transport measurements are used to relate junction depths to sheet resistance and their dependence on annealing temperature and time. For spike annealing, junction leakage and adequate activation limits the minimum practical temperature while diffusion limits the maximum practical temperature for formation of shallow junctions.

At the current pace of semiconductor technology development, transistor dimensions in advanced IC products will approach the range of a few tens of nanometers within the next decade. This presents a major challenge for our understanding of defects and diffusion in these tiny devices during processing. In response, an almost explosive growth in research on process physics has taken place at universities, national institutes and industry research labs worldwide. The central issue is the phenomenon of nonequilibrium diffusion driven by processing steps such as oxide growth, high concentration gradients of impurities, and annealing of damage caused by ion implantation. Nonequilibrium diffusion arises from perturbations to the natural thermal equilibrium concentrations of point defects - interstitial atoms and vacancies - in the silicon crystal. This paper gives a snapshot of our current understanding of the atomic-scale interactions between point defects and impurity atoms, extended defects and interfaces, as revealed by recent experimental and theoretical studies. The paper emphasizes the important role played by defect cluster ripening during transient enhanced diffusion and dopant activation.