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The resistive switching behavior in SiOx-based phase change memory devices confined by few nanometer wide graphene nanogaps is investigated. Our experiments and analysis reveal that the switching dynamics is not only determined by the commonly observed bias voltage dependent set and reset times. We demonstrate that an internal time scale, the dead time, plays a fundamental role in the system's response to various driving signals. We associate the switching behavior with the formation of microscopically distinct SiOx amorphous and crystalline phases between the graphene electrodes. The reset transition is attributed to an amorphization process due to a voltage driven self-heating; it can be triggered at any time by appropriate voltage levels. In contrast, the formation of the crystalline ON state is conditional and only occurs after the completion of a thermally assisted structural rearrangement of the as-quenched OFF state which takes place within the dead time after a reset operation. Our results demonstrate the technological relevance of the dead time rule which enables a zero bias access of both the low and high resistance states of a phase change memory device by unipolar voltage pulses. [ABSTRACT FROM AUTHOR]

Graphene nanogap electrodes have been of recent interest in a variety of fields, ranging from molecular electronics to phase change memories. Several recent reports have highlighted that scaling graphene nanogaps to even smaller sizes is a promising route to more efficient and robust molecular and memory devices. Despite the significant interest, the operating and scaling limits of these electrodes are completely unknown. In this paper, we report on our observations of consistent voltage driven resistance switching in sub-5 nm graphene nanogaps. We find that such electrical switching from an insulating state to a conductive state occurs at very low currents and voltages (0.06 μA and 140 mV), independent of the conditions (room ambient, low temperatures, as well as in vacuum), thus portending potential limits to scaling of functional devices with carbon electrodes. We then associate this phenomenon to the formation and rupture of carbon chains. Using a phase change material in the nanogap as a demonstrator device, fabricated using a self-alignment technique, we show that for gap sizes approaching 1 nm the switching is dominated by such carbon chain formation, creating a fundamental scaling limit for potential devices. These findings have important implications, not only for fundamental science, but also in terms of potential applications. [ABSTRACT FROM AUTHOR]

A phase change nanowire holds a promise for nonvolatile memory applications, but its transition mechanism has remained unclear due to the analytical difficulties at atomic resolution. Here we obtain a deeper understanding on the phase transition of a single crystalline Ge2Sb2Te5 nanowire (GST NW) using atomic scale imaging, diffraction, and chemical analysis. Our cross-sectional analysis has shown that the as-grown hexagonal close-packed structure of the single crystal GST NW transforms to a metastable face-centered cubic structure due to the atomic migration to the pre-existing vacancy layers in the hcp structure going through iterative electrical switching. We call this crystal structure transformation "metastabilization", which is also confirmed by the increase of set-resistance during the switching operation. For the set to reset transition between crystalline and amorphous phases, high-resolution imaging indicates that the longitudinal center of the nanowire mainly undergoes phase transition. According to the atomic scale analysis of the GST NW after repeated electrical switching, partial crystallites are distributed around the core-centered amorphous region of the nanowire where atomic migration is mainly induced, thus potentially leading to low power electrical switching. These results provide a novel understanding of phase change nanowires, and can be applied to enhance the design of nanowire phase change memory devices for improved electrical performance. [ABSTRACT FROM AUTHOR]

Phase-change memory (PCM) is an importantclass of data storage, yet lowering the programming current of individualdevices is known to be a significant challenge. Here we improve theenergy-efficiency of PCM by placing a graphene layer at the interfacebetween the phase-change material, Ge2Sb2Te5(GST), and the bottom electrode (W) heater. Graphene-PCM(G-PCM) devices have ∼40% lower RESET current compared to controldevices without the graphene. This is attributed to the graphene asan added interfacial thermal resistance which helps confine the generatedheat inside the active PCM volume. The G-PCM achieves programmingup to 105cycles, and the graphene could further enhancethe PCM endurance by limiting atomic migration or material segregationat the bottom electrode interface. [ABSTRACT FROM AUTHOR]

Phasechange materials are widely considered for application innonvolatile memories because of their ability to achieve phase transformationin the nanosecond time scale. However, the knowledge of fast crystallizationdynamics in these materials is limited because of the lack of fastand accurate temperature control methods. In this work, we have developedan experimental methodology that enables ultrafast characterizationof phase-change dynamics on a more technologically relevant melt-quenchedamorphous phase using practical device structures. We have extractedthe crystallization growth velocity (U) in a functionalcapped phase change memory (PCM) device over 8 orders of magnitude(10–10< U< 10–1m/s) spanning a wide temperature range (415 < T< 580 K). We also observed direct evidence of non-Arrhenius crystallizationbehavior in programmed PCM devices at very high heating rates (>108K/s), which reveals the extreme fragility of Ge2Sb2Te5in its supercooled liquid phase. Furthermore,these crystallization properties were studied as a function of deviceprogramming cycles, and the results show degradation in the cell retentionproperties due to elemental segregation. The above experiments areenabled by the use of an on-chip fast heater and thermometer calledas microthermal stage (MTS) integrated with a vertical phase changememory (PCM) cell. The temperature at the PCM layer can be controlledup to 600 K using MTS and with a thermal time constant of 800 ns,leading to heating rates ∼108K/s that are closeto the typical device operating conditions during PCM programming.The MTS allows us to independently control the electrical and thermalaspects of phase transformation (inseparable in a conventional PCMcell) and extract the temperature dependence of key material propertiesin real PCM devices. [ABSTRACT FROM AUTHOR]

A central issue of nanoelectronics concerns their fundamentalscaling limits, that is, the smallest and most energy-efficient devicesthat can function reliably. Unlike charge-based electronics that areprone to leakage at nanoscale dimensions, memory devices based onphase change materials (PCMs) are more scalable, storing digital informationas the crystalline or amorphous state of a material. Here, we describea novel approach to self-align PCM nanowires with individual carbonnanotube (CNT) electrodes for the first time. The highly scaled andspatially confined memory devices approach the ultimate scaling limitsof PCM technology, achieving ultralow programming currents (∼0.1μA set, ∼1.6 μA reset), outstanding on/off ratios(∼103), and improved endurance and stability atfew-nanometer bit dimensions. In addition, the powerful yet simplenanofabrication approach described here can enable confining and probingmany other nanoscale and molecular devices self-aligned with CNT electrodes. [ABSTRACT FROM AUTHOR]

Integration of nanowires into functional devices withhigh yieldsand good reliability turned out to be a lot more challenging and provedto be a critical issue obstructing the wide application of nanowire-baseddevices and exploitation of their technical promises. Here we demonstratea relatively easy macrofabrication of a nanowire-based imaging circuitryusing a recently developed nanofabrication technique. Extremely longand polymer encapsulated semiconducting nanowire arrays, mass-producedusing the iterative thermal drawing, facilitate the integration process;we manually aligned the fibers containing selenium nanowires overa lithographically defined circuitry. Controlled etching of the encapsulatingpolymer revealed a monolayer of nanowires aligned over an area of1 cm2containing a 10 × 10 pixel array. Each light-sensitivepixel is formed by the contacting hundreds of parallel photoconductivenanowires between two electrodes. Using the pixel array, alphabeticcharacters were identified by the circuitry to demonstrate its imagingcapacity. This new approach makes it possible to devise extremelylarge nanowire devices on planar, flexible, or curved substrates withdiverse functionalities such as thermal sensors, phase change memory,and artificial skin. [ABSTRACT FROM AUTHOR]

The self-assembly of Ge1Sb2Te4nanowires (NWs) for phase change memories application wasachievedby metal organic chemical vapor deposition, catalyzed by Au nanoislandsin a narrow range of temperatures and deposition pressures. In theoptimized conditions of 400 °C, 50 mbar, the NWs are Ge1Sb2Te4single hexagonal crystals. Phase changememory switching was reversibly induced by nanosecond current pulsesthrough metal-contacted NWs with threshold voltage of about 1.35 V. [ABSTRACT FROM AUTHOR]

The resistive switching behavior in SiO x -based phase change memory devices confined by few nanometer wide graphene nanogaps is investigated. Our experiments and analysis reveal that the switching dynamics is not only determined by the commonly observed bias voltage dependent set and reset times. We demonstrate that an internal time scale, the dead time, plays a fundamental role in the system's response to various driving signals. We associate the switching behavior with the formation of microscopically distinct SiO x amorphous and crystalline phases between the graphene electrodes. The reset transition is attributed to an amorphization process due to a voltage driven self-heating; it can be triggered at any time by appropriate voltage levels. In contrast, the formation of the crystalline ON state is conditional and only occurs after the completion of a thermally assisted structural rearrangement of the as-quenched OFF state which takes place within the dead time after a reset operation. Our results demonstrate the technological relevance of the dead time rule which enables a zero bias access of both the low and high resistance states of a phase change memory device by unipolar voltage pulses.

A phase change nanowire holds a promise for nonvolatile memory applications, but its transition mechanism has remained unclear due to the analytical difficulties at atomic resolution. Here we obtain a deeper understanding on the phase transition of a single crystalline Ge 2 Sb 2 Te 5 nanowire (GST NW) using atomic scale imaging, diffraction, and chemical analysis. Our cross-sectional analysis has shown that the as-grown hexagonal close-packed structure of the single crystal GST NW transforms to a metastable face-centered cubic structure due to the atomic migration to the pre-existing vacancy layers in the hcp structure going through iterative electrical switching. We call this crystal structure transformation "metastabilization", which is also confirmed by the increase of set-resistance during the switching operation. For the set to reset transition between crystalline and amorphous phases, high-resolution imaging indicates that the longitudinal center of the nanowire mainly undergoes phase transition. According to the atomic scale analysis of the GST NW after repeated electrical switching, partial crystallites are distributed around the core-centered amorphous region of the nanowire where atomic migration is mainly induced, thus potentially leading to low power electrical switching. These results provide a novel understanding of phase change nanowires, and can be applied to enhance the design of nanowire phase change memory devices for improved electrical performance.