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As the computing paradigm has shifted toward edge computing, improving the security of edge devices is attracting significant attention. However, because edge devices have limited resources in terms of power and area, it is difficult to apply a conventional cryptography system to protect them. On the other hand, as a simple security application, a physical unclonable function (PUF) can be implemented without power and area problems because it provides a security key by utilizing process variations without additional external circuits. Ferroelectric tunnel junctions (FTJs) are 2-terminal devices that store information by changing the resistance of a ferroelectric material, where the resistance is determined by the polarization states of the ferroelectric domains. Because polycrystalline ferroelectric materials have a multi-domain nature, domain variation can also be used as a randomness source to induce cell-to-cell variations along with process variations. In this paper, we demonstrate PUF operations of a low-power, small area 16 × 16 hafnium oxide (pure-HfO

As interest in artificial intelligence (AI) and relevant hardware technologies has been developed rapidly, algorithms and network structures have become significantly complicated, causing serious power consumption issues because an enormous amount of computation is required. Neuromorphic computing, a hardware AI technology with memory devices, has emerged to solve this problem. For this application, multilevel operations of synaptic devices are important to imitate floating point weight values in software AI technologies. Furthermore, weight transfer methods to desired weight targets must be arranged for off-chip training. From this point of view, we fabricate 32 × 32 memristor crossbar array and verify the 3-bit multilevel operations. The programming accuracy is verified for 3-bit quantized levels by applying a reset-voltage-control programming scheme to the fabricated TiO

To analyze the effect of the intrinsic variations of the memristor device on the neuromorphic system, we fabricated 32 × 32 Al2O3/TiO x -based memristor crossbar array and implemented 3 bit multilevel conductance as weight quantization by utilizing the switching characteristics to minimize the performance degradation of the neural network. The tuning operation for 8 weight levels was confirmed with a tolerance of ±4 μA (±40 μS). The endurance and retention characteristics were also verified, and the random telegraph noise (RTN) characteristics were measured according to the weight range to evaluate the internal stochastic variation effect. Subsequently, a memristive neural network was constructed by off-chip training with differential memristor pairs for the Modified National Institute of Standards and Technology (MNIST) handwritten dataset. The pre-trained weights were quantized, and the classification accuracy was evaluated by applying the intrinsic variations to each quantized weight. The intrinsic variations were applied using the measured weight inaccuracy given by the tuning tolerance, RTN characteristics, and the fault device yield. We believe these results should be considered when the pre-trained weights are transferred to a memristive neural network by off-chip training.

As the computing paradigm has shifted toward edge computing, improving the security of edge devices is attracting significant attention. However, because edge devices have limited resources in terms of power and area, it is difficult to apply a conventional cryptography system to protect them. On the other hand, as a simple security application, a physical unclonable function (PUF) can be implemented without power and area problems because it provides a security key by utilizing process variations without additional external circuits. Ferroelectric tunnel junctions (FTJs) are 2-terminal devices that store information by changing the resistance of a ferroelectric material, where the resistance is determined by the polarization states of the ferroelectric domains. Because polycrystalline ferroelectric materials have a multi-domain nature, domain variation can also be used as a randomness source to induce cell-to-cell variations along with process variations. In this paper, we demonstrate PUF operations of a low-power, small area 16 × 16 hafnium oxide (pure-HfOx)-based FTJ array using certain metrics. It is clear that the proposed array consisting of scaled FTJs has adequate randomness for security applications such that the array-level PUF operations are robust against model-based machine learning attacks.

As interest in artificial intelligence (AI) and relevant hardware technologies has been developed rapidly, algorithms and network structures have become significantly complicated, causing serious power consumption issues because an enormous amount of computation is required. Neuromorphic computing, a hardware AI technology with memory devices, has emerged to solve this problem. For this application, multilevel operations of synaptic devices are important to imitate floating point weight values in software AI technologies. Furthermore, weight transfer methods to desired weight targets must be arranged for off-chip training. From this point of view, we fabricate 32 × 32 memristor crossbar array and verify the 3-bit multilevel operations. The programming accuracy is verified for 3-bit quantized levels by applying a reset-voltage-control programming scheme to the fabricated TiO x /Al2O3-based memristor array. After that, a synapse composed of two differential memristors and a fully-connected neural network for modified national institute of standards and technology (MNIST) pattern recognition are constructed. The trained weights are post-training quantized in consideration of the 3-bit characteristics of the memristor. Finally, the effect of programming error on classification accuracy is verified based on the measured data, and we obtained 98.12% classification accuracy for MNIST data with the programming accuracy of 1.79% root-mean-square-error. These results imply that the proposed reset-voltage-control programming scheme can be utilized for a precise tuning, and expected to contribute for the development of a neuromorphic system capable of highly precise weight transfer.

Brain-inspired neuromorphic systems have attracted much attention as new computing paradigms for power-efficient computation. Here, we report a silicon synaptic transistor with two electrically independent gates to realize a hardware-based neural network system without any switching components. The spike-timing dependent plasticity characteristics of the synaptic devices are measured and analyzed. With the help of the device model based on the measured data, the pattern recognition capability of the hardware-based spiking neural network systems is demonstrated using the modified national institute of standards and technology handwritten dataset. By comparing systems with and without inhibitory synapse part, it is confirmed that the inhibitory synapse part is an essential element in obtaining effective and high pattern classification capability.