1. Design Space Exploration of Hardware Spiking Neurons for Embedded Artificial Intelligence
- Author
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Benoit Miramond, Nassim Abderrahmane, Edgar Lemaire, Laboratoire d'Electronique, Antennes et Télécommunications (LEAT), Université Nice Sophia Antipolis (... - 2019) (UNS), COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-COMUE Université Côte d'Azur (2015-2019) (COMUE UCA)-Centre National de la Recherche Scientifique (CNRS)-Université Côte d'Azur (UCA), Thales Research and Technology [Palaiseau], THALES, and ANR-19-P3IA-0002,3IA@cote d'azur,3IA Côte d'Azur(2019)
- Subjects
FOS: Computer and information sciences ,0209 industrial biotechnology ,Computer science ,Design space exploration ,Cognitive Neuroscience ,Computation ,Action Potentials ,02 engineering and technology ,[INFO.INFO-NE]Computer Science [cs]/Neural and Evolutionary Computing [cs.NE] ,Machine Learning ,symbols.namesake ,020901 industrial engineering & automation ,Computer Systems ,Artificial Intelligence ,0202 electrical engineering, electronic engineering, information engineering ,Information coding Neuromorphic computing Hardware architecture Power consumption Embedded systems ,Humans ,Neural and Evolutionary Computing (cs.NE) ,Neurons ,Spiking neural network ,Artificial neural networks ,Spiking neural networks ,Computers ,business.industry ,Computer Science - Neural and Evolutionary Computing ,Brain ,Abstract machine ,Neuromorphic engineering ,symbols ,020201 artificial intelligence & image processing ,Neural Networks, Computer ,business ,Neural coding ,Computer hardware ,Von Neumann architecture - Abstract
International audience; Machine learning is yielding unprecedented interest in research and industry, due to recent success in many applied contexts such as image classification and object recognition. However, the deployment of these systems requires huge computing capabilities, thus making them unsuitable for embedded systems. To deal with this limitation, many researchers are investigating brain-inspired computing, which would be a perfect alternative to the conventional Von Neumann architecture based computers (CPU/GPU) that meet the requirements for computing performance, but not for energy-efficiency. Therefore, neuromorphic hardware circuits that are adaptable for both parallel and distributed computations need to be designed. In this paper, we focus on Spiking Neural Networks (SNNs) with a comprehensive study of information coding methods and hardware exploration. In this context, we propose a framework for neuromorphic hardware design space exploration, which allows to define a suitable architecture based on application-specific constraints and starting from a wide variety of possible architectural choices. For this framework, we have developed a behavioral level simulator for neuromorphic hardware architectural exploration named NAXT. Moreover, we propose modified versions of the standard Rate Coding technique to make trade-offs with the Time Coding paradigm, which is characterized by the low number of spikes propagating in the network. Thus, we are able to reduce the number of spikes while keeping the same neuron’s model, which results in an SNN with fewer events to process. By doing so, we seek to reduce the amount of power consumed by the hardware. Furthermore, we present three neuromorphic hardware architectures in order to quantitatively study the implementation of SNNs. One of these architectures integrates a novel hybrid structure: a highly-parallel computation core for most solicited layers, and time-multiplexed computation units for deeper layers. These architectures are derived from a novel funnel-like Design Space Exploration framework for neuromorphic hardware.
- Published
- 2020