1. Trapping mechanisms in insulated-gate GaN power devices: Understanding and characterization techniques.
- Author
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Yang, Shu, Liu, Shenghou, Lu, Yunyou, and Chen, Kevin J.
- Subjects
POWER transistors ,POWER field effect transistors ,TRANSISTORS ,FIELD-effect transistors ,SINGLE electron transistors - Abstract
In addition to surface- and buffer-trapping, interface/border trapping and the consequent V
TH shift in insulated-gate GaN power transistors could also cause RON increase, due to the reduced gate overdrive. This work reports on a systematic study of the trapping mechanisms in normally-on/off insulated-gate GaN transistors subjected to dynamic (AC) and static (DC) gate stress. The fast dynamic characterizations featuring an ultrashort measurement delay of 10−7 s minimize the recovery during measurement and enable a quantitative evaluation of VTH shift-induced RON increase. By analyzing the time-resolved instability in normally-on MIS-HEMT and normally-off MIS-FET with fully recessed barrier, we elucidate several key mechanisms including: (i) recessing the polarized III-nitride barrier layer can suppress VTH shift during ON/OFF switching; (ii) AC stress, which has more practical implication for lifetime projection for power switching applications, produces smaller VTH shift and RON increase comparing to DC stress; (iii) Sufficient gate overdrive at ON state and lower channel resistance in normally-on MIS-HEMT allow a better tolerance to VTH shift. Primary trapping effects in an insulated-gate GaN power transistor. [ABSTRACT FROM AUTHOR]- Published
- 2017
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