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GaN power switching transistors featuring MIS- and MOS-gate structures are highly preferred over the Schottky-gate counterpart, because of suppressed gate leakage, enlarged gate swing, and more scalable threshold voltage. Nevertheless, MIS-/MOS-gate GaN devices are confronted with stability and reliability challenges, which arise from interface traps at the critical dielectric/III-nitride interface, as well as bulk traps inside the gate dielectric including border traps near the critical interface. In this work, we present several key techniques toward reliable MIS-/MOS-gate GaN power devices, including advanced interface engineering technology, gate structure optimizations for high-performance/stability normally-off GaN power transistors, and long-lifetime gate dielectric technology. Schematic cross sections of GaN-based MIS-HEMT and MOS-channel-HEMT. [ABSTRACT FROM AUTHOR]

In addition to surface- and buffer-trapping, interface/border trapping and the consequent VTH shift in insulated-gate GaN power transistors could also cause RON increase, due to the reduced gate overdrive. This work reports on a systematic study of the trapping mechanisms in normally-on/off insulated-gate GaN transistors subjected to dynamic (AC) and static (DC) gate stress. The fast dynamic characterizations featuring an ultrashort measurement delay of 10−7 s minimize the recovery during measurement and enable a quantitative evaluation of VTH shift-induced RON increase. By analyzing the time-resolved instability in normally-on MIS-HEMT and normally-off MIS-FET with fully recessed barrier, we elucidate several key mechanisms including: (i) recessing the polarized III-nitride barrier layer can suppress VTH shift during ON/OFF switching; (ii) AC stress, which has more practical implication for lifetime projection for power switching applications, produces smaller VTH shift and RON increase comparing to DC stress; (iii) Sufficient gate overdrive at ON state and lower channel resistance in normally-on MIS-HEMT allow a better tolerance to VTH shift. Primary trapping effects in an insulated-gate GaN power transistor. [ABSTRACT FROM AUTHOR]