10 results on '"Raghavan, Praveen"'
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2. IMEC N7, N5 and beyond: DTCO, STCO and EUV insertion strategy to maintain affordable scaling trend
3. High-volume manufacturing compatible dry development rinse process (DDRP): patterning and defectivity performance for EUVL
4. Design and pitch scaling for affordable node transition and EUV insertion scenario
5. Large marginal 2D self-aligned via patterning for sub-5nm technology
6. The effect of patterning options on embedded memory cells in logic technologies at iN10 and iN7
7. Standard cell design in N7: EUV vs. immersion
8. DTCO at N7 and beyond: patterning and electrical compromises and opportunities
9. Low track height standard-cells enable high-placement density and low-BEOL cost (Conference Presentation)
10. In-design and signoff lithography physical analysis for 7/5nm (Erratum)
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