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The rapid development of quantum technology challenges the security of modern cryptography, which causes concern from the cryptographic community about the quantum implementation of cryptographic algorithms, as it is an important component of many quantum attacks. In this paper, the construction of quantum circuits for Camellia block cipher is investigated. Firstly, a 4-bit S-box is derived from the hardware circuit of the Camellia S-box, which divides the S-box circuit into three parts. Then, based on the rearranged circuit, as well as the implementation of the CCCNOT gate, the construction of the NCT-based circuit for the Camellia S-box is researched. Meanwhile, combined with the observations on the rearranged S-box circuit and the discussion on the in-place implementation of different matrices, a quantum circuit for the Camellia S-box with lower T-depth is presented. As an application, the various S-box circuits are used to construct quantum circuits for the Camellia family. The results reveal that the memory-efficient and depth-efficient quantum circuits of Camellia can be constructed with lower T-depth and T · M value. Besides, for each instance of Camellia, compared with existing state-of-the-art implementation with lowest T-depth and T · M value, the depth-efficient circuit designed in this work only costs about 35% of the qubits. [ABSTRACT FROM AUTHOR]

This work researches the implementation of the AES family with Pauli-X gates, CNOT gates and Toffoli gates as the underlying quantum logic gate set. First, the properties of quantum circuits are investigated, as well as the influence of Pauli-X gates, CNOT gates and Toffoli gates on the performance of the circuits constructed with those gates. Based on these properties and the observations on the hardware circuits built by Boyar et al. and Zou et al., it is possible to construct quantum circuits for AES's Substitution-box (S-box) and its inverse (S-box - 1 ) by rearranging the classical implementation to three parts. Since the second part is treated as a 4-bit S-box in this paper and can be dealt with by existing tools, a heuristic is proposed to search optimized quantum circuits for the first and the third parts. In addition, considering the number of parallelly executed S-boxes, the trade-offs between the qubit consumption and T · M values for the round function and key schedule of AES are studied. As a result, quantum circuits of AES-128, AES-192 and AES-256 can be constructed with 269, 333 and 397 qubits, respectively. If more qubits are allowed, quantum circuits that outperform state-of-the-art schemes in the metric of T · M value for the AES family can be reported, and it needs only 474, 538 and 602 qubits for AES-128, AES-192 and AES-256, respectively. [ABSTRACT FROM AUTHOR]

In recent years, the quantum implementation of symmetric ciphers has received much attention. In this paper, we investigate the construction of quantum circuits based on different gate sets for the SM4 block cipher, which is the national standard of commercial cryptography of China and is standardized in ISO/IEC. First, we construct reversible circuits using Pauli-X gates, CNOT gates and Toffoli gates (i.e., the NCT gate set) for the SM4 S-box, based on which we design two circuits for the SM4 S-box with Clifford+T gates by applying the quantum And gate and existing decomposition scheme of the Toffoli gate, respectively. In addition, we propose a new in-place 1 implementation for the linear transformation in the SM4 round function. Finally, taking the qubit consumption and the T · M value (the product of qubit consumption and nonlinear gate depth of a quantum circuit) as metrics, we investigate the application of various circuits we designed to the construction of quantum circuits for SM4. The results show that we can always construct a subroutine/stand-alone circuit based on the NCT gate set, or based on Clifford+T gates for SM4 with fewer qubits or lower T · M value than existing state-of-the-art implementations. [ABSTRACT FROM AUTHOR]