1. Development of 3T eDRAM gain cells for enhancing read margin and data retention
- Author
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Shyam Akashe, Saurabh Khandelwal, Tarushree Varshney, and This paper was supported by ITM (Gwalior) with the collaboration of Cadence System Design (Bangalore, India).
- Subjects
Very-large-scale integration ,Engineering ,Dynamic random-access memory ,business.industry ,020208 electrical & electronic engineering ,Transistor ,Electrical engineering ,02 engineering and technology ,eDRAM ,01 natural sciences ,PMOS logic ,law.invention ,law ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,Electronic engineering ,Hardware_INTEGRATEDCIRCUITS ,logic compatible eDRAM ,data retention ,3T gain cell ,enhanced read margin ,static power ,nanotechnology ,Electrical and Electronic Engineering ,Data retention ,010306 general physics ,business ,Dram ,NMOS logic - Abstract
This paper presents three transistors (3T) based Dynamic Random Access Memory (DRAM) cell in which noise, static power, and data retention voltage (DRV) have been reduced. The spesified parameters in the proposed eDRAM gain cell were improved by connecting the source of storage device to the read word line signal instead of supply voltage. As we all know, power consumption plays a vital role in VLSI design and thus, it is enumerated among the top challenges for the semiconductor chip industries. With the intention to maintain the performance of write operation, we diminish DRV and increase the read margin of eDRAM cell with our designed circuit which is introduced as “A Boosted 3T eDRAM gain cell”. It is a kind of eDRAM cell that utilizes a read word line (RWL) via three PMOS transistors instead of NMOS transistors. PMOS devices are preferred as they have radically less gate leakage current, which confer better results for data retention and thus, boost up the read margin of the cell. Simulation results have been obtained by using Cadence Virtuoso Tool at 45 nm technology for the proposed model. Based on simulation results we can conclude that the parameters of the proposed eDRAM gain cell essentially improved as compared with convertional eDRAM gain cell and the achieved parameters are as follows: static power is 0.767 pW, DRV is 142.009 mV and noise is 8.421 nV/Hz1/2.
- Published
- 2016