Search

Scaling of bulk MOSFET faces great challenges in nanoscale integration technology by producing short channel effect which leads to increased leakage. FinFET has become the most promising substitute to bulk CMOS technology because of reducing short channel effect. Dual-gate FinFET can be designed either by shorting gates on either side for better performance or both gates can be controlled independently to reduce the leakage and hence power consumption. A six transistor SRAM cell based on independent-gate FinFET technology is described in this paper for simultaneously reducing the active and standby mode power consumption. A work is focused on the independent gate FinFET technology as this mode provides less power consumption, less area consumption and low delay as compared to other modes. Leakage current and power consumption in independent gate FinFET is compared with tied gate or shorted gate FinFET SRAM cell. Moreover, delay has been estimated in presented SRAM cells. Further, leakage reduction technique is applied to independent gate FinFET 6T SRAM cell.

This paper presents three transistors (3T) based Dynamic Random Access Memory (DRAM) cell in which noise, static power, and data retention voltage (DRV) have been reduced. The spesified parameters in the proposed eDRAM gain cell were improved by connecting the source of storage device to the read word line signal instead of supply voltage. As we all know, power consumption plays a vital role in VLSI design and thus, it is enumerated among the top challenges for the semiconductor chip industries. With the intention to maintain the performance of write operation, we diminish DRV and increase the read margin of eDRAM cell with our designed circuit which is introduced as “A Boosted 3T eDRAM gain cell”. It is a kind of eDRAM cell that utilizes a read word line (RWL) via three PMOS transistors instead of NMOS transistors. PMOS devices are preferred as they have radically less gate leakage current, which confer better results for data retention and thus, boost up the read margin of the cell. Simulation results have been obtained by using Cadence Virtuoso Tool at 45 nm technology for the proposed model. Based on simulation results we can conclude that the parameters of the proposed eDRAM gain cell essentially improved as compared with convertional eDRAM gain cell and the achieved parameters are as follows: static power is 0.767 pW, DRV is 142.009 mV and noise is 8.421 nV/Hz1/2.