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Indian Regional Navigation Satellite System (IRNSS) is a satellite based navigation system developed by Indian Space Research Organization (ISRO). The positional accuracy of IRNSS is limited by several errors including ionospheric delay. Ionospheric delay can be estimated with precise calculation of total electron content (TEC). However, TEC is biased by multipath and thermal noise. Therefore, multipath and thermal noise free relative TEC measurements are made and compared with two other methods, namely, code TEC and IRNSS Receiver Software (IRS) techniques. In this investigation L5 (1176.45 MHz) and S1 (2492.028 MHz) signals from IRNSS 1A to 1G satellites are considered. The results indicate that relative TEC estimation technique removes the multipath and thermal noise from the TEC measurements. Further, the TEC for signals coming from various IRNSS satellites are evaluated by calculating the standard deviation (SD). In the analysis the data is divided into segments with duration of 1 h each. The results indicate that SDs for the relative TEC estimation (2.5 TECU in case of IRNSS 1B) are lesser than the other two techniques indicating the relative TEC can be used in the receiver for the estimation of ionospheric delay. Further, the high ratio of the operating frequencies indicates a better TEC estimation.

This paper presents three transistors (3T) based Dynamic Random Access Memory (DRAM) cell in which noise, static power, and data retention voltage (DRV) have been reduced. The spesified parameters in the proposed eDRAM gain cell were improved by connecting the source of storage device to the read word line signal instead of supply voltage. As we all know, power consumption plays a vital role in VLSI design and thus, it is enumerated among the top challenges for the semiconductor chip industries. With the intention to maintain the performance of write operation, we diminish DRV and increase the read margin of eDRAM cell with our designed circuit which is introduced as “A Boosted 3T eDRAM gain cell”. It is a kind of eDRAM cell that utilizes a read word line (RWL) via three PMOS transistors instead of NMOS transistors. PMOS devices are preferred as they have radically less gate leakage current, which confer better results for data retention and thus, boost up the read margin of the cell. Simulation results have been obtained by using Cadence Virtuoso Tool at 45 nm technology for the proposed model. Based on simulation results we can conclude that the parameters of the proposed eDRAM gain cell essentially improved as compared with convertional eDRAM gain cell and the achieved parameters are as follows: static power is 0.767 pW, DRV is 142.009 mV and noise is 8.421 nV/Hz1/2.

There are represented the algorithms of estimation of radiation source in angular-measuring and differential distance-measuring radio systems with minimal amount of carriers moving around, taking into account the errors of receiving points location on a basis of adaptive filtering with method expanded state vector split. There are represent the results of static simulation.

There is shown applicability of quasi-static method for analysis of differential equations of single-circuit autodyne generator. We propose the methodology of quasi-static calculation of autodyne response taking into account of members of higher approximation order. The estimation of calculation inaccuracy in case of quasi-static method application is given, conditions of stability of the system of autodyne generator–reflecting object are considered, and comparative calculation of autodyne response for a cases of application of zeroth and tenth approximations.

Scaling of bulk MOSFET faces great challenges in nanoscale integration technology by producing short channel effect which leads to increased leakage. FinFET has become the most promising substitute to bulk CMOS technology because of reducing short channel effect. Dual-gate FinFET can be designed either by shorting gates on either side for better performance or both gates can be controlled independently to reduce the leakage and hence power consumption. A six transistor SRAM cell based on independent-gate FinFET technology is described in this paper for simultaneously reducing the active and standby mode power consumption. A work is focused on the independent gate FinFET technology as this mode provides less power consumption, less area consumption and low delay as compared to other modes. Leakage current and power consumption in independent gate FinFET is compared with tied gate or shorted gate FinFET SRAM cell. Moreover, delay has been estimated in presented SRAM cells. Further, leakage reduction technique is applied to independent gate FinFET 6T SRAM cell.

This paper presents an overview of the process and design capabilities of state-of-the-art in the field of microwave solid state switches. The paper describes types of solid state switches, switch specifications, a review of technological advances in this area. The overview results indicate that AlGaN/GaN MMICs including solid state switches are realizable.