Search

A peak-voltage detection circuit based on a differential comparison structure is proposed to synchronize the control and the input signal. The detection circuit is hence free of reset signals for the sampling capacitors. Furthermore, a two-channel parallel sample and hold structure (i.e., S/H circuit) is used, and a correlated double sampling technique is used, in combination with the ping-pong technique, to sample the signal value and offset voltage within one sample cycle. Consequently, the parallel connected S/H structure can not only extract the offset voltage of the op-amp but also effectively reduce the detection error, which is caused by circuit noise and leakage current. Measurements of the implemented peak detector show that in the case that the detection signal frequency is 20 kHz and the amplitude is 10 mV, the detection error is decreased to 30 µV with the equivalent output noise of 71 n V / H z . [ABSTRACT FROM AUTHOR]