Search

Abstract Production of high-aspect-ratio silicon (Si) nanowire-based anode for lithium ion batteries is challenging particularly in terms of controlling wire property and geometry to improve the battery performance. This report demonstrates tunable optimization of inductively coupled plasma reactive ion etching (ICP-RIE) at cryogenic temperature to fabricate vertically-aligned silicon nanowire array anodes with high verticality, controllable morphology, and good homogeneity. Three different materials [i.e., photoresist, chromium (Cr), and silicon dioxide (SiO2)] were employed as masks during the subsequent photolithography and cryogenic ICP-RIE processes to investigate their effects on the resulting nanowire structures. Silicon nanowire arrays with a high aspect ratio of up to 22 can be achieved by tuning several etching parameters [i.e., temperature, oxygen/sulfur hexafluoride (O2/SF6) gas mixture ratio, chamber pressure, plasma density, and ion energy]. Higher compressive stress was revealed for longer Si wires by means of Raman spectroscopy. Moreover, an anisotropy of lattice stress was found at the top and sidewall of Si nanowire, indicating compressive and tensile stresses, respectively. From electrochemical characterization, half-cell battery integrating ICP-RIE-based silicon nanowire anode exhibits a capacity of 0.25 mAh cm−2 with 16.67% capacity fading until 20 cycles, which has to be improved for application in future energy storage devices.

Abstract Performing long-term cell observations is a non-trivial task for conventional optical microscopy, since it is usually not compatible with environments of an incubator and its temperature and humidity requirements. Lensless holographic microscopy, being entirely based on semiconductor chips without lenses and without any moving parts, has proven to be a very interesting alternative to conventional microscopy. Here, we report on the integration of a computational parfocal feature, which operates based on wave propagation distribution analysis, to perform a fast autofocusing process. This unique non-mechanical focusing approach was implemented to keep the imaged object staying in-focus during continuous long-term and real-time recordings. A light-emitting diode (LED) combined with pinhole setup was used to realize a point light source, leading to a resolution down to 2.76 μm. Our approach delivers not only in-focus sharp images of dynamic cells, but also three-dimensional (3D) information on their (x, y, z)-positions. System reliability tests were conducted inside a sealed incubator to monitor cultures of three different biological living cells (i.e., MIN6, neuroblastoma (SH-SY5Y), and Prorocentrum minimum). Altogether, this autofocusing framework enables new opportunities for highly integrated microscopic imaging and dynamic tracking of moving objects in harsh environments with large sample areas.

Abstract This paper reports on the direct qualitative and quantitative performance comparisons of the field-effect transistors (FETs) based on vertical gallium nitride nanowires (GaN NWs) with different NW numbers (i.e., 1–100) and diameters (i.e., 220–640 nm) fabricated on the same wafer substrate to prove the feasibility of employing the vertical 3D architecture concept towards massively parallel electronic integration, particularly for logic circuitry and metrological applications. A top-down approach combining both inductively coupled plasma dry reactive ion etching (ICP-DRIE) and wet chemical etching is applied in the realization of vertically aligned GaN NWs on metalorganic vapor-phase epitaxy (MOVPE)-based GaN thin films with specific doping profiles. The FETs are fabricated involving a stack of n-p-n GaN layers with embedded inverted p-channel, top drain bridging contact, and wrap-around gating technology. From the electrical characterization of the integrated NWs, a threshold voltage (V th) of (6.6 ± 0.3) V is obtained, which is sufficient for safely operating these devices in an enhancement mode (E-mode). Aluminium oxide (Al2O3) grown by atomic layer deposition (ALD) is used as the gate dielectric material resulting in nearly-zero gate hysteresis (i.e., forward and backward sweep V th shift (ΔV th) of ~0.2 V). Regardless of the required device processing optimization for having better linearity profile, the upscaling capability of the devices from single NW to NW array in terms of the produced currents could already be demonstrated. Thus, the presented concept is expected to bridge the nanoworld into the macroscopic world, and subsequently paves the way to the realization of innovative large-scale vertical GaN nanoelectronics.