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The double gate junctionless transistor (DG-JLT) has become the most promising device in sub nano-meter regime. DGJLT based circuits have improved performance and simpler fabrication than their inversion mode counterparts. This paper demonstrates the design of different analog and digital circuits using DGJLT. Amplifiers and inverters are the basic building block of electronic ICs. A MOS amplifier converts the variation of the gate to source voltage to a small current under transconductance and hence, the output voltage. A single-stage amplifier and differential amplifier have been designed with junctionless-double-gate (JL-DG) MOSFET. Trans-conductance, output voltage, and gain have been investigated using ATLAS 2D device simulator. The inverter is the primary logic gate that can be used to verify the device's response in digital applications. Further, CMOS inverter have been designed using JL-DG MOSFET, and its performance parameters such as switching voltage, noise margin, and logic delay have been analyzed. A switching voltage of 0.43 V, noise margin of 0.265 V, and a delay of 19.18 psec have been obtained for the basic cell. CMOS inverter using JL-DG MOSFET at 20 nm technology node have prompted better performance results. Thus, The JL-DG MOSFET has a bright future in low-power analog and digital applications.

Flip chip (FC) light emitting diodes (LEDs) are considered to be more promising in solid state lighting as compared to wire bonded LEDs. For solid-state lighting, thermal management is a very critical factor to enhance the device’s performance. In the Flip Chip Light Emitting Diode (LED), the active region is the main source of heat generation. This heat is to be conducted through different layers to the heat sink. The adhesive layer and bump assembly cause heat dissipation because of their low conductivity values and poor transparency and hence cause degradation in performance of FC-LEDs. In this paper, thermal analysis of flip chip LED is done to find out how material, size of die and bumps affect the thermal performance of FC-LED. A flip chip LED structure is modeled on a GaN substrate. Different material properties of silicon, gold, and aluminum have been studied to perform the thermal analysis and to see the effects of different die sizes, bump sizes, and adhesive materials. Thermal analysis of the high-power FC LED by using the Finite Element Method is done on Ansys Software. The FC structure and its meshing design are presented.Temperature variation with different sizes of bump, chip-die and different adhesives (silver filled epoxy, Au-Sn, Pb-Sn) on flip chip LED is discussed. The result shows that thermal heat is directly proportional to the size of the bump and the type of adhesive material selected also affects the performance of FC-LEDto some extent.

Low power, low cost, less chip area, and high speed have become the requirements in the present generation of electronic circuits in nano-sacle technology. Due to the requirement of high speed, small silicon chip area, and low power consumption of VLSI circuits, CMOS technology is scaled down. This paper proposes a novel circuit to improve the circuit performance of large fan-in footless domino. A weak keeper is controlled in this paper by a novel silicon based network controller known as a keeper controlling network. The keeper controlling network includes a silicon PMOS transistor and an odd number of inverters. The PMOS transistor in the keeper controlling network acts as a switch. Toward the beginning of the evaluation phase, if any one of its inputs of the proposed design is high then it deactivates the silicon keeper transistor to improve the speed of the circuit. Once all inputs of the proposed circuits are low in the evaluation phase, it turns ON the keeper transistor which increases the circuit’s robustness. Simulations are done for 4, 8, 16, and 32 inputs OR gate of proposed and existing circuits by utilizing 90 nm CMOS technology. The proposed circuit limits the power utilization by 31.82 % and improves the noise robustness by 0.99 % in comparison with the existing HS-domino circuit for 32-inputs.

The metamaterial absorber intends the structure of the solar cell to boost its internal parameters like the short-circuit current density (Jsc), Voc and efficiency. In this work, A novel single band polarization insensitive metamaterial (MTM) absorber is designed and investigated for solar cell energy harvesting applications. The proposed MTM unit cell is made of three layers named as glass bottom layer, layer 1, layer 2 and a top metal conducting layer. All these layers are stacked on a glass substrate with a thickness of 2.5 nm. The proposed MTM unit cell and its variations makes it possible to have a higher absorption rate of greater than 75% across the full range of visible spectrum. By analyzing the unit cell, it was found that it delivers a tunable character and maximum absorption of >75% over a wide range of frequency (534–672 THz) in the visible regime. The parametric study of overall size of the MTM absorber was analyzed over the frequency range from 450 to 750 THz. This design responds to a near perfect absorption of 99.99% at a resonance frequency of 560–570 THz and also has >90% absorption between 570 and 650 THz frequencies which is almost half of the visible range. Based on the similar works in the existing literature it has been found that the proposed MTM unit cell design was found out to be the best for high-efficiency solar cell energy harvesting applications.