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Your search keyword '"*INTEGRATED circuit packaging"' showing total 2 results
Start Over Descriptor "*INTEGRATED circuit packaging" Topic wafer level packaging Publication Year Range Last 50 years Journal solid state technology
2 results on '"*INTEGRATED circuit packaging"'

1. Reveal previously invisible defects and contaminants in advanced packaging applications: A new illumination technology compares favorably to conventional bright field illumination.

Author

SINGH, GURVINDER

Subjects
*INDUSTRIAL contamination prevention, *INTEGRATED circuit packaging, *WAFER level packaging, *ELECTRIC properties of polymers, *SEMICONDUCTOR industry
Abstract

The article discusses the development of a new optical technique to reveal invisible defects and contaminants in advanced packaging applications. It mentions that the technique can reveal contaminants that escape inspection technologies in many advanced packaging applications like wafer level packaging (WLP). It mentions challenges in advanced packaging applications like redistribution layer (RDL) line widths, use of metal and organic polymers.

Published
2017

2. Smart management in the sub-fab improves safety, reliability, cost and yield.

Author

Chambers, Andrew

Subjects
*WAFER level packaging, *INTEGRATED circuit packaging, *DYNAMIC random access memory, *CHEMICAL vapor deposition, *FLAMMABILITY
Abstract

The article discusses improvement in safety, reliability, cost and yield with smart management in the sub-fab. Topics discussed include increase in number of 300mm wafer production-class fabs in operation worldwide, increasing application of high-flow chemical vapor deposition (CVD) processes in production of DRAM and other devices, and dilution of exhaust gases to mitigate flammability risks.

Published
2017

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