Search

In this work, the impact of the channel doping density on the low-frequency noise of silicon Gate-All-Around (GAA) Vertical Nanowire (VNW) pMOSFETs on Silicon-on-Insulator (SOI) substrates will be described and discussed. It is demonstrated that the dominant fluctuation mechanism of the 1/f noise in the subthreshold regime changes from number (Δn) to mobility (Δμ) fluctuations with increasing p-type doping density of the silicon nanowires. At the same time, the lowest input-referred voltage noise Power Spectral Density is observed for an intermediate boron concentration in the nanowire of 5 × 10^18 cm^(-3).

In this work, Gate-All-Around Nanowire MOSFETs have been studied at very low temperatures. DC behaviors have been investigated in the linear operation and saturation regions, giving access to several analog parameters. Static characteristics at 4.2 K and low polarization exhibit step- like variations of the drain current, which can be linked to energy subband scattering. First results on the impact of quantum transport mechanism on the low frequency noise are shown. Finally the low frequency noise spectroscopy has led to the identification of silicon film traps.

Made available in DSpace on 2021-06-25T10:32:25Z (GMT). No. of bitstreams: 0 Previous issue date: 2021-11-01 In this work, the DC behavior of AlGaN/GaN Metal-Insulator-Semiconductor high electron mobility transistors (MO(I)SHEMTs) with two different gate dielectrics (Al2O3 and Si3N4) is analyzed through the experimental comparison of their basic and analog parameters. The transistors with Si3N4 insulator are more closely related to the normally-off devices (less negative threshold voltage) and less affected by the short channel effects (better DIBL behavior). Although the devices with Si3N4 layer presented a double conduction, that results in anomalous transconductance behavior, it is more suitable for analog applications since the Al2O3 devices suffer large self-heating. The very high gate leakage of Si3N4 MISHEMT degrades the subthreshold regime, which decreases the transistor efficiency at weak inversion. On the other hand, the devices with Si3N4 insulator present relatively large Early voltage and consequently high intrinsic voltage gain in strong inversion, reaching 84 V/V (38.5 dB). Even at high temperatures the intrinsic voltage gain is practically the same, degrading only 1.5 dB from 25 °C to 150 °C for a long channel device. UNESP Sao Paulo State University LSI/PSI/USP University of Sao Paulo Imec, Kapeldreef 75 UNESP Sao Paulo State University

Low frequency noise (LFN) studies are carried out on n-channel gate all around nanowire (GAA NW) FETs. Measurements both as a function of applied polarisation at fixed temperature and conserving the same drain current bias points as a function of temperature are performed, to investigate the predominant flicker noise fluctuation mechanism and to execute low frequency noise spectroscopy allowing to identify the active traps in the depletion area of the devices. The good correlation between the normalized drain current noise SId / Id2 and the transconductance to drain current ratio squared (gm/Id)2 enables to establish that the 1/f noise is related to the carrier number fluctuations mechanisms for all investigated temperatures. The study of the generation recombination (GR) noise as a function of temperature confirms the presence of a GR component for which the characteristic frequency is independent on the applied voltage and present variation with the temperature, suggesting that they are related to active traps located in the Si film. Active traps related to hydrogen and divacancies were identified.

Low frequency noise measurements are used as a non-destructive diagnostic tool in order to evaluate the quality of the gate oxide and the silicon film of sub-10 nm triple-gate Silicon-on-Insulator (SOI) FinFETs. It was found that the carrier number fluctuations explain the 1/ f noise in moderate inversion for n- and p-FinFETs, which allows estimating the gate oxide trap densities. The noise spectroscopy with respect to temperature (study of the generation-recombination noise) led to the identification of the traps located in the transistors silicon film.

Made available in DSpace on 2018-12-11T16:42:27Z (GMT). No. of bitstreams: 0 Previous issue date: 2016-09-01 This paper presents an experimental analysis of the analog application figures of merit: the intrinsic voltage gain (AV) and unit gain frequency, focusing on the performance comparison between silicon triple gate pFinFET devices, which were processed on both Si and Silicon-On-Insulator (SOI) substrates. The high temperature (from 25 °C to 150 °C) influence and different channel lengths and fin widths were also taken into account. While the temperature impact on the intrinsic voltage gain (AV) is limited, the unit gain frequency was strongly affected due to the carrier mobility degradation at higher temperatures, for both p- and n-type FinFET structures. In addition, the pFinFETs showed slightly larger AV values compared to the n-type counterparts, whereby the bulk FinFETs presented a higher dispersion than the SOI FinFETs. LSI/PSI/USP University of Sao Paulo, Av. Prof. Luciano Gualberto, trav. 3 no 158 UNESP imec, Kapeldreef 75 Dept. of Solid State Sciences Ghent University, Krijgslaan 281 S1 EE Depart. KU Leuven, Kasteelpark Arenberg 10 UNESP

The floating body retention time is investigated on fully depleted SOI devices with UTBOX. The retention is occurring through the junctions and strongly assisted by defects in the junction space charge region during the holding state at a negative gate voltage. For standard devices with a gate overlap, the junction field is high and the dominant mechanism in this case is the generation by band-to-band tunneling. For optimized extensionless devices with lower junction field, the Shockley–Read–Hall generation enhanced by the field and Poole–Frenkel mechanism takes over the band-to-band tunneling. Therefore, reducing the concentration of Si impurities closer to the junctions is the key to approach an ideal retention time only due to band-to-band tunneling with the Si bandgap as the energy barrier for tunneling.

This work aims to analyze the impact of the Ground Plane (GP) on a new generation of the dynamic threshold (DT2) operation in Ultra-thin Body and Buried Oxide (UTBB) SOI nMOSFETs. The DT2, using a short-circuit between the gate and the substrate contact, the enhanced dynamic threshold (eDT), where the substrate bias is a multiple value of the gate bias (VB = k × VG, k = 1,2,…,5), and the inverse eDT (with VG = k × VB) were compared to the conventional mode with grounded substrate. Although the improvement of the DT2 mode observed for devices with GP is lower, they presented lower short channel effects, mainly for shorter channel lengths. Regarding the direct and inverse eDT modes, a stronger dynamic threshold (DT) effect on devices with GP also results in better DC parameters such as lower subthreshold swing and higher maximum transconductance.

In this work, the electrical properties of p-GeSn/n-Ge diodes are investigated in order to assess the impact of defects at the interface between Ge and GeSn using temperature-dependent current–voltage and capacitance–voltage measurements. These structures are made from GeSn epitaxial layers grown by CVD on Ge with in situ doping by Boron. As results, an average ideality factor of 1.2 has been determined and an activation energy comprised between 0.28 eV and 0.30 eV has been extracted from the temperature dependence of the reverse-bias current. Based on the comparison with numerical results obtained from device simulations, we explain this activation energy by the presence of traps located near the GeSn/Ge interface.

The analysis of the low-frequency noise of fully-depleted Silicon-On-Insulator (SOI) ultra-thin body and Ultra-Thin Buried Oxide (UTBOX) MOSFETs with different gate stacks, Si film thicknesses and extension architecture is performed. It was revealed that the extension architecture is the main factor affecting the drain current and low frequency noise behavior of the devices studied. It is revealed that the 1/f noise of extensionless MOSFETs appears to be higher than for standard ones, especially when the back interface is biased towards accumulation. The latter is accompanied by the lower drain current of extensionless devices in comparison to standard ones. Moreover, the Lorentzians accompanying the Linear Kink Effect that were revealed for standard MOSFETs, were not observed for extensionless devices. The latter is ascribed to the different architecture of the source/drain regions, which affect source/drain-body junctions characteristics and free charge carrier concentration.

In this paper the NBTI degradation has been studied in pMOS transistors with ultra-thin high-k dielectric subjected to a millisecond anneal for ultra-shallow junction implantation using different laser powers. An ultrafast characterization technique has been developed with the aim of acquiring the threshold voltage (Vth) shift in relaxation times as short as possible once the electrical stress is removed. It has been observed that increasing the millisecond anneal temperature reduce the NBTI degradation. These results have been explained in the context of the emission and capture probability maps of the defects.

The impact of cryogenic temperature operation (10 K) on the short channel effects and low frequency noise was analysed on strained and unstrained n-channel FinFET transistors fabricated on silicon on insulator (SOI) substrates in order to evaluate the devices static performances and to study the low frequency noise mechanisms. The main electrical parameters are investigated and it is evidenced that even at very low temperatures, the strain-engineering techniques boost the devices performances in terms of mobility, threshold voltage, access resistances and drain saturation currents. The DIBL effect, Early voltage and the intrinsic gain are ameliorated only for the short channel devices. A drawback, however, is that slightly improved turn-on capabilities may be noted for standard channel devices compared to strained ones. Low frequency noise measurements show that the carrier number fluctuations dominate the flicker noise in weak inversion even at 10 K operation. Access resistance noise contributions were evidenced in strong inversion.

This work aims to analyze the retention time as a limiting factor for the application of 1T-DRAM cell in future CMOS nodes. Two approaches are proposed in order to improve the retention time: by the source/drain structure engineering or by applying a pulsed back gate bias. This work analyses the upgrade of the retention time by reducing the GIDL effect when the source/drain is underlapped with the gate. A lower retention time is observed for shorter channel length even optimizing the constant back gate bias, but the underlap devices present better results. The Gate-Induced Drain Leakage (GIDL), its amplification by a narrower base of the bipolar transistor inherent in the MOS structure and the longer effective channel length are the responsible mechanisms for the degradation of the retention time in both holding-0 and reading-0. The use of the pulsed back gate bias during write-1, as well as its variation, were analyzed. The pulsed bias case presents an improvement of 5% of the retention time and no difference was observed when the pulsed back gate level was varied.

The influence of different spacer lengths and tilt-implantation on underlapped devices compared to the standard S/D junctions (with Lightly Doped Drain – LDD) on fully depleted (FD) SOI MOSFETs with Ultra-Thin Buried Oxide (UTBOX) at room and high temperatures is explored. It is shown that devices with longer spacers and no LDD implantation increase the underlap region between the gate edge and the S/D regions, increase the immunity to short channel effects and improve the analog performance even at high temperatures. However, the lateral dopant diffusion can reduce or suppress the underlap formation, mainly for smaller spacer length. Tilt-implanted devices exhibit the same trend as the devices with LDD. The angled implantation favors the dopant diffusion into the underlap regions, which degrades the transistor performance.

International audience; In this paper, DC and noise measurements on strained and unstrained SOI p-FinFETs were performed at cryogenic temperatures (10 K) in order to evaluate the device performances and study the low frequency noise mechanisms. The main electrical parameters (threshold voltage, subthreshold swing, mobility, etc.) are investigated and compared to those found at 80 K and 300 K. The low frequency noise analysis clearly shows that from 300 K to 10 K, the carriers number fluctuation dominates the flicker noise in the channel in weak inversion, while the access resistances noise contribution prevails in strong inversion. 1/fc noise has been observed with c varying with the temperature, which implies a non-uniformity of the active trap density in the oxide depth. The noise of the access resistances at 300 K originates from mobility fluctuations, while at low temperature operation it seems to have a trapping-detrapping origin.

In this work the influence of different stress techniques and proton irradiation on the off-state leakage current is investigated for p- and n-channel Multiple Gate MOSFETs (MuGFETs). Four different splits are evaluated: unstrained, uniaxially stressed, biaxially stressed and the combination of both types of stress. For nMuGFETs, the higher the stress effectiveness the higher is the GIDL due to band gap narrowing. However for p-channel devices, the gate leakage current is higher than band-to-band tunneling and it dominates the drain current in the off-state region. After proton irradiation all the n-channel devices present a worse behavior. Off-state leakage current for nMuGFETs was degraded by radiation due to the increase of the back gate leakage current generated by the increase of the interface charge density at the back interface. For p-channel devices, the radiation did not show any influence in off-state leakage current, since the gate oxide thickness is very thin and therefore the radiation has no influence on the gate current, which is the dominant effect in the pMuGFETs off-state region.

This paper investigates the front and back gate bias influence on current sense margin and retention time in Ultra-Thin Buried Oxide (UTBOX) Fully Depleted Silicon On Insulator (FDSOI) devices used as a FBRAM (floating body random access memory) cell through simulations and experimental results. This work aims to gain insight into the mechanisms involved into FBRAM operation and optimize the front and back gate biases for achieving the best retention time and current sense margin. The writing ‘1’, through BJT effect, and writing ‘0’, by using capacitive coupling, were verified. We demonstrated that, during the holding, the operation mode of the interfaces is an important factor for the best condition for achieving both a higher current sense margin and a longer retention time, which should be with the front gate in accumulation mode and the back gate in depletion mode. It was also observed that depending on gate bias applied during the hold operation, there are two mechanisms involved in retention time. For less negative gate voltage the retention time is limited by recombination, whereas for more negative gate voltage the generation mechanisms take place. Moreover, the retention time showed more sensitivity to the back gate voltage than the current sense margin.

This work examines the influence of the annealing time at 350 °C to the reverse current and capacitance characteristics of p + /n junction diodes fabricated by platinum assisted dopant activation. The reverse current and capacitance characteristics are first separated into bulk and peripheral components. The bulk or volume component is further analyzed in terms of diffusion and generation currents which constitute the physical components of the bulk reverse current. This allows the extraction of the generation and recombination lifetimes as well as the effective position of the energy levels of the generation–recombination centers. The results indicate that for the used active area geometry, the periphery and the bulk current components coexist in comparable magnitudes. Annealing for 10 min provides the lowest reverse current with the highest generation and recombination lifetimes. Higher annealing times deteriorate the diode due to the formation of defects within the depletion region which reduce the generation and recombination lifetimes.

In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a non-planar structure is experimentally studied in triple-gate FinFETs. The drain current, transconductance, resistance, threshold voltage, subthreshold swing and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DT mode and the standard biasing configuration. Moreover, for the first time, the important figures of merit for the analog performance such as transconductance-over-drain current, output conductance, Early voltage and intrinsic voltage gain will be studied experimentally and through three-dimensional (3-D) numerical simulations for different channel doping concentrations in triple-gate DTMOS FinFETs. The results indicate that the DTMOS FinFETs always yield superior characteristics and larger transistor efficiency. In addition, DTMOS devices with a high channel doping concentration exhibit much better analog performance compared to the normal operation mode, which is desirable for high performance low-power/low-voltage applications.

This work studies the gate-induced drain leakage (GIDL) in p- and n-MuGFET structures with different TiN metal gate thickness and high-k gate dielectrics. As a result of this analysis, it was observed that a thinner TiN metal gate showed a larger GIDL due to the different gate oxide thickness and a reduced metal gate work function. In addition, replacing SiON by a high-k dielectric (HfSiON) results for nMuGFETs in a decrease of the GIDL. On the other hand, the impact of the gate dielectric on the GIDL for p- channel MuGFETs is marginal. The effect of the channel width was also studied, whereby narrow fin devices exhibit a reduced GIDL current in spite of the larger vertical electric field expected for these devices. Finally, comparing the effect of the channel type, an enhanced GIDL current for pMuGFET devices was observed.

This work presents the analog performance of n-type triple-gate MuGFETs with high- k dielectrics and TiN gate material fabricated in 45° rotated SOI substrates comparing their performance with standard MuGFETs fabricated without substrate rotation. Different fin widths are studied for temperatures ranging from 250 K up to 400 K. The results of transconductance, output conductance, transconductance over drain current ratio, intrinsic voltage gain and unit-gain frequency are studied. It is observed that the substrate rotation improves the carrier mobility of narrow MuGFETs at any temperature because of the changing in the conduction plane at the sidewalls from (1 1 0) to (1 0 0). For lower temperatures, the improvement of the carrier mobility of rotated MuGFETs is more noticeable as well as the rate of mobility improvement with the temperature decrease is larger. The output conductance is weakly affected by the substrate rotation. Although this improvement in the transconductance of rotated MuGFETs is negligibly transferred to the intrinsic voltage gain, the unity-gain frequency of rotated device is improved due to the larger carrier mobility in the entire range of temperatures studied.

The LKE (Linear Kink Effect) and BGI (Back-Gate-Induced) Lorentzians present in the drain current noise spectra of fully-depleted tri-gate n - and p FinFETs, fabricated on sSOI and SOI substrates with HfSiON/SiO 2 gate dielectric are described. It is shown that the analysis of the parameters of LKE and BGI Lorentzians allows to find the values of ( С eq / m ′ β 2 ), β and [ j EVB /( m ′ β ) 2 ] where С eq is the body-source capacitance, m ′ ≈ 1, β is the body factor and j EVB is the density of the EVB current flowing through the gate dielectric. As a result, the following effects were observed for the first time: (i) ( С eq / m ′ β 2 ) decreases with increasing gate overdrive voltage | V ∗ | and depends sub-linearly on the effective fin width W eff under strong inversion conditions; (ii) in depletion and weak inversion where ( С eq / β 2 ) is independent of | V ∗ | the proportionality ( С eq / β 2 ) ∝ W eff is observed for an effective width W eff ⩾ 0.87 μm while ( С eq / β 2 ) becomes independent on W eff for W eff β for the FinFETs investigated is higher than for their planar counterparts; (iv) in spite of the fact that strain affects the barrier height at the Si/SiO 2 interface, the EVB current densities j EVB for sSOI and SOI devices are equal; (v) the values of j EVB for the HfSiON/SiO 2 -devices are much higher than for the HfО 2 /SiO 2 -ones studied previously. It is also shown that the gate overdrive voltage | V ∗ | at which the LKE Lorentzians start to appear is as low as 0.25 V.

This work characterizes the analog performance of SOI n-MuGFETs with HfSiO gate dielectric and TiN metal gate with respect to the influence of the high- k post-nitridation, TiN thickness and device rotation. A thinner TiN metal gate is found favorable for improved analog characteristics showing an increase in intrinsic voltage gain. The devices where the high- k material is subjected to a nitridation step indicated a degradation of the Early voltage ( V EA ) values which resulted in a lower voltage gain. The 45° rotated devices have a smaller V EA than the standard ones when a HfSiO dielectric is used. However, the higher transconductance of these devices, due to the increased mobility in the (1 0 0) sidewall orientation, compensates this V EA degradation of the voltage gain, keeping it nearly equal to the voltage gain values of the standard devices.

This work investigates the harmonic distortion (HD) in 2-MOS balanced structures composed of triple gate FinFETs. HD has been evaluated through the determination of the third-order harmonic distortion (HD3), since this represents the major non-linearity source in balanced structures. The 2-MOS structures with devices of different channel lengths ( L ) and fin widths ( W fin ) have been studied operating in the linear region as tunable resistors. The analysis was performed as a function of the gate voltage, aiming to verify the correlation between operation bias and HD3. The physical origins of the non-linearities have been investigated and are pointed out. Being a resistive circuit, the 2-MOS structure is generally projected for a targeted on-resistance, which has also been evaluated in terms of HD3. The impact of the application of biaxial strain has been studied for FinFETs of different dimensions. It has been noted that HD3 reduces with the increase of the gate bias for all the devices and this reduction is more pronounced both in narrower and in longer devices. Also, the presence of strain slightly diminishes the non-linearity at a similar bias. However, a drawback associated with the use of strain engineering consists in a significant reduction of the on-resistance with respect to unstrained devices.

The impact of the titanium nitride (TiN) gate electrode thickness has been investigated in n- and p-channel SOI multiple gate field-effect transistors (MuGFETs) through low-frequency noise, charge pumping and static measurements as well as capacitance–voltage curves. The results suggest that a thicker TiN metal gate electrode gives rise to a higher EOT, a lower mobility and a higher interface trap density. The devices have also been studied for different back gate biases where the GIFBE onset occurs at lower front-gate voltage for thinner TiN metal gate thickness and at higher V GF . In addition, it is demonstrated that post-deposition nitridation of the MOCVD HfSiO gate dielectric exhibits an unexpected trend with TiN gate electrode thickness, where a continuous variation of EOT and an increase on the degradation of the interface quality are observed.

Identifying the trap configuration is essential for understanding non-volatile memory device performance and reliability. In this paper, an accurate approach to determine the trap distribution in the charged layer is presented. The analysis is done by Trap Spectroscopy by Charge Injection and Sensing (TSCIS) technique [1] varying charge injection time and gate voltage independently. Varying time determines the physical charge injection distance. The conversion of time into distance is done based on theoretical modeling simplified to only electron capturing from Shockley–Read–Hall (SRH) statistics. Direct tunneling of the electrons from quantized energy levels in inverted Si channels to the oxide traps is considered with a WKB approximation. This approach gives the electron scanning rate in SiO 2 as 0.19 nm/decade, which is consistent with previous noise/direct tunneling analyses. The effect of the residual charge on the potential energy barrier for the electron tunneling is also accounted for in the electron scanning distance calculation by including Gauss’ law. Considering the charge voltage determines the trap energy level, and we can finally obtain the trap distribution ‘map’ inside the oxide. This TSCIS technique is applied to profile the oxide trap density in oxide stacks for flash memory application successfully. Traps located spatially as far as 3 nm from the Si/SiO 2 interface can be probed with 1000 s of charge injection time in case of a 0.87 nm SiO 2 /10 nm Al 2 O 3 stack.

The study of the low frequency (1/ f ) noise of strained Si 0.8 Ge 0.2 p-channel MOSFETs with poly Si/HfSiO x gate stacks is presented. Apart from the reduced threshold voltage, improved maximum transconductance and increased low-field mobility offered by the strained SiGe, the 1/ f noise was observed to be considerably lower than in the Si control devices. The 1/ f noise characteristics were likely originated by carrier number fluctuations (Δ n model) for both the strained SiGe and Si control pMOSFETs. This is consistent with the proposed model for high-k MOSFETs based on correlated number-mobility fluctuations theory. Despite the much worse high-k gate stack quality characterized by gate leakage and charge pumping, the relative reduction (up to 10×) in the noise for the strained SiGe over Si control with high-k is preserved, as was observed in the past for strained SiGe and Si control devices having SiO 2 gate dielectric, likely attributed to the existence of the Si cap layer.

The Lorentzian-like noise induced by Electron Valence Band (EVB) tunneling has been investigated in n- and p-channel multiple-gate field-effect transistors (MuGFETs), processed on silicon-on-insulator (SOI) and strained SOI (sSOI) substrates. The effect has been studied for different back-gate and front-gate biases and as a function of the device geometry. Similar as for wide fully depleted SOI transistors, this type of excess low-frequency noise is found when the back gate is biased in accumulation. However, it is shown that the characteristic time constant of the Lorentzian cannot be modeled assuming a uniform EVB tunneling current across the gate area of the MuGFETs. This indicates an impact of the three-dimensional nature of the device architecture on the so-called linear kink effects. In addition, it is demonstrated that the tensile strain in sSOI MuGFETs also yields a change in the Lorentzian parameters, associated with changes in the EVB tunneling current.

The temperature influence on the gate-induced floating body effect (GIFBE) in fully depleted (FD) silicon-on-insulator (SOI) nMOSFETs is investigated, based on experimental results and two-dimensional numerical simulations. The GIFBE behavior will be evaluated taking into account the impact of carrier recombination and of the effective electric field mobility degradation on the second peak in the transconductance (gm). This floating body effect is also analyzed as a function of temperature. It is shown that the variation of the studied parameters with temperature results in a “C” shape of the threshold voltage corresponding with the second peak in the gm curve.

For fully-depleted SOI MOSFETs, fabricated in standard and strained 65 nm technologies, it is observed that the drain current I normalized for the device length L and width W levels off at sufficiently high gate voltage overdrives. Also the normalized drain current 1/ f noise spectral density S I shows a plateau value for high front gate voltages. For both strained and non-strained devices there exists a relation between the two plateau values and a y ∼ ( x ) 1/4 law is found for the experimental data where x = S I plateau ( L 3 / WN ot ) , y = I plateau ( L /t W), S I plateau and I plateau are the plateau values of S I and I , respectively, and N ot is the density of the oxide traps responsible for the 1/ f noise observed. Compared to standard SOI the use of strained SOI (sSOI) increases the magnitude of the plateau and makes its dependence on the device geometry more pronounced, while the impact of a strained contact etch stop layer (sCESL) is limited. The experimental observations are explained by taking into consideration the field and geometry dependence of the mobility and the influence of negative oxide charges on the drain current.

This work studies the impact of uniaxial, biaxial and combined uniaxial–biaxial strain on the linearity of nMOSFETs from a 65 nm fully depleted (FD) SOI technology. The total harmonic distortion (THD) and third-order harmonic distortion (HD3) will be used as figures of merit. Operation in saturation and triode regimes will be the focus. When biased in the saturation region short-channel devices have been used and biased as single-transistor amplifiers. In this case, at low voltage bias the use of any kind of strain improves the THD in comparison to standard SOI. When operating in linear region as a quasi-linear resistor longer devices were studied. For operation in linear regime the HD3 is nearly the same for all devices and no clear strain influence can be found at similar bias condition. If a target on-resistance is considered, the use of biaxially or combined unxially–biaxially strained films can provide a reduction on the required gate voltage overdrive or a reduction on the device channel width without degrading the HD3.

In this paper, the appearance of gate induced floating body effects in triple gate SOI nFinFETs with TiN/SiON and TiN/HfO2 gate stacks is investigated. Different floating body effects (FBEs) are found to appear under moderate accumulation back gate bias (VBG) conditions in devices with wide and long enough geometries. In particular, a second peak in the linear transconductance (gmf), associated with electron valence band (EVB) direct tunneling, is observed in TiN/SiON devices for front gate voltages (VFG) around 0.8 V. Interestingly, in spite of showing about two orders of magnitude lower total gate current, a second peak in gmf is also found in TiN/HfO2 devices for VFG around 1.1 V. Under the accumulation VBG conditions in which FBEs are observed, front gate switch drain current (ID) transients are also appreciated. Interestingly, a change in the shape of ID transients is observed for VFG conditions in which EVB majority carriers are injected into the floating fin. The ID transients, as well as the second peak of gmf and other FBEs, are found to gradually diminish for strong accumulation VBG conditions or reduced geometry dimensions. © 2007 Elsevier Ltd. All rights reserved.

In partially depleted (PD) silicon-on-insulator (SOI) MOSFETs with thin gate oxides, a particular effect named linear kink effect (LKE) occurs, which is due to the fact that the body potential is strongly affected by majority carriers injected in the body by the electron valence-band (EVB) tunneling through the ultra-thin gate oxide. This unexpected phenomenon induces a second peak in the transconductance gm curve and an excess Lorentzian noise in the low-frequency noise spectrum. A model based on RC filtered shot noise due to the EVB tunneling current and the forward current of the source-body junction was recently proposed at room temperature. In this work, the focus is on the temperature impact on the Lorentzian noise induced by valence-band electron tunneling in partially depleted SOI p-MOSFETs. For the first time, a Lorentzian noise filtered by the same RC network as the shot noise of the EVB tunneling current has been observed in the LKE operation at low temperature. It seems that the EVB tunneling current can also accompany an excess Lorentzian noise due to traps localized at the Si/gate oxide interface. A simple extension of the model developed by Lukyanchikova et al. is proposed and validated by experimental results from room temperature down to 80 K.

The low-frequency (LF) noise of n-MOSFETs with a 1.5 nm SiON gate oxide is studied for different gate materials, namely, a polycrystalline (poly) silicon gate, a fully nickelsilicided (FUSI) gate and a NiSi FUSI gate deposited on 10 cycles of HfO2. The principal aim is to identify the most likely origin of the predominant 1/f noise in the thin gate oxide devices by investigating the impact of the gate electrode processing. It is reported that the lowest input-referred voltage noise spectral density (SVG) in linear operation for a gate voltage at the threshold voltage is found for the FUSI transistor, while adding 10 cycles of HfO2 enhances markedly the noise magnitude. The 1/f noise characteristic behaves according to the number fluctuations theory so that the results are interpreted in terms of trapping and de-trapping of channel carriers by defects in the gate dielectric layer. Therefore, the marked effect of the gate material is at present ascribed to the different trap density in the vicinity of the gate-SiON interface, which is derived from the LF noise spectra.

This work presents the analog performance of nMOS triple-gate FinFETs with high-κ dielectrics, TiN gate material and undoped body from DC measurements. Different fin widths and devices with and without halo implantation are explored. No halo FinFETs can achieve extremely large gain and improved unity gain frequency at similar channel length than halo counterparts. The FinFETs with 110 nm long channel achieve an intrinsic gain of 25 dB. Extremely large Early voltages have been measured on long channel nMOS with no halo and relatively wide fins compared to the results usually reported in the literature. The large Early voltage obtained suggests that the devices operate in the onset of volume inversion due to the low doping level of the device body.

An overview is given on the low-frequency (LF) noise of silicon-on-insulator (SOI) devices and technologies. In the first two parts, noise mechanisms specific for SOI are discussed, namely, the front–back-gate coupling in fully-depleted MOSFETs and the Lorentzian noise overshoot in floating-body operating transistors. In the next part, the impact of the technology (SOI substrate, gate stack processing, isolation module, …) on the LF noise is described. From this, it is derived that scaling below the 0.25 μm CMOS node did not result in the anticipated reduction of the 1/f noise with tfox or t fox 2 . This is related to the increasing amount of nitrogen incorporated in the thin SiON front gate oxides with thickness tfox. In the case of high-κ dielectrics it is frequently observed that these have a higher trap density compared to SiO2. On the other hand, today’s multigate SOI transistors seem to give rise to similar gate oxide trap densities and hence, 1/f noise, than their single-gate counterparts. In the last part, operational and circuit aspects will be discussed, which might have a beneficial impact on the LF noise performance.

The defects related to the gate-dielectric in high-K-MOSFETs are studied using the 1/f noise technique. Three different types of gate electrodes were used for this purpose - poly-Si, metal (TiN/TaN) and fully Ni Silicided (FUSI) electrodes with Hf-based oxides as the gate dielectric layer. All the three types of devices show a specific behavior near the gate electrode-dielectric interface when the trap profiles are assessed using f× S I spectra. The tunneling depths were calculated and it was found that the high-K oxide (bulk) layers are being probed. From the drain current spectra S I vs. drain current I D of the various gate material devices at given depths, it may be inferred that the concentration of oxygen-vacancy-related defects can significantly influence the 1/f noise performance, which can explain the differences observed in noise between the gate electrodes. Comparison of FUSI gated devices, with various percentages of Hf in the dielectric layer, shows comparable noise levels (S VG ), indicating a minor dependence on Hf-content in the gate dielectric layer.

The impact of using a twin-gate (TG) configuration on the Electron Valence-Band (EVB) tunnelling-related floating-body effects has been studied in partially depleted (PD) SOI MOSFETs belonging to a 0.13 μm CMOS technology. In particular, the influence on the so-called linear kink effects (LKEs), including the second peak in the linear transconductance ( g m ) and the associated Lorentzian noise overshoot was investigated. It is shown that while there is a modest reduction of the second g m peak, the noise overshoot may be reduced by a factor of 2. At the same time, little asymmetry is observed when switching the role of the slave and the master transistor, in contrast to the case of the impact ionization related kink effects. Two-dimensional numerical simulations support the observations and show that both the g m , the second g m peak and the body potential are changed in the TG structure compared with a single transistor.

This work studies the effect of halo implantation on the electrical characteristics of deep-submicrometer partially depleted SOI nMOSFETs during low temperature and floating body operation. Parameters such as the drain induced barrier lowering (DIBL) and the device thermal resistance have been investigated. It is shown that the combination of floating body operation with halo implantation degrades the DIBL in the temperature range studied (90 K–300 K) in comparison to devices that did not received this implantation. The halo region causes a more pronounced negative output conductance than for the transistors without a halo implantation. An estimation of the temperature rise for a given dissipated power in both types of devices is made, based on the thermal resistance, which is derived from the output characteristics in function of the temperature.

Evidence is provided for excess tunneling 1/f γ noise into trap states in a 5 nm HfO 2 layer deposited on 2.1 nm thermal SiO 2 . As such, it is a nice illustration of the McWhorter type of flicker noise. The interaction of the HfO 2 traps with inversion layer carriers gives rise to an excess 1/f γ component below 100 Hz typically, corresponding to a y > 1. In contrast, the background 1/f γ' noise of the SiO 2 layer is characterized by a γ' < 1 and dominates the high-frequency part of the spectra. The excess fluctuations cause several peaks in the noise spectral density as a function of the gate bias or drain current. The fact that more than one resonance peak is found suggests tunneling to or from different discrete defect states or bands of energy levels.

In this work we assess the effect of low-energy nitrogen implantation for dual-gate oxide thickness formation. A comparison of transistor performance, 1/f noise and oxide reliability is made between 3.5 nm thick oxides fabricated by nitrogen ion implantation followed by dry oxidation and a reference oxide grown by dry oxidation followed by annealing in nitric oxide (NO oxide). The results show that the ion-implanted samples have lower oxide charges, lower 1/f noise, good reliability and sufficient boron penetration immunity.

This overview discusses the impact of ionizing irradiation on the static, the transient and the low-frequency noise characteristics of deep submicron partially depleted (PD) silicon-on-insulator (SOI) transistors. It is demonstrated that, while from a total ionizing dose (TID) damage viewpoint the technology is suitable for space applications, there is still a marked performance degradation. Evidence is provided that at least two basic mechanisms are involved. One is related to the radiation-induced hole trapping in the field oxide, giving rise to a subthreshold leakage current. In addition, the occurrence of majority carrier injection by electron valence-band (EVB) tunneling gives rise to some unexpected front–back channel coupling effects. A second yet unknown mechanism gives rise to a length-dependent response of the static device parameters, pointing to a laterally non-uniform charging of the gate oxide and/or the silicon body.

In this paper, the impact of the channel length ( L ) on the parameters of the electron valence band (EVB) tunneling induced Lorentzian noise is described for partially-depleted (PD) silicon-on-insulator (SOI) MOSFETs. The Lorentzian time constant at a fixed gate overdrive voltage tends to increase for the shortest lengths studied, while the plateau amplitude of the current noise spectral density ( S I (0)) levels off at short L . A different behaviour is observed for the n- compared with the p-channel transistors, while a strong effect will be shown by the presence of a HALO implantation, used to control the short channel effect. It is demonstrated that the observations can be qualitatively explained by considering the Lorentzian noise as the result of the RC filtered shot noise accompanying the EVB tunneling current and the forward current of the source-body junction. For explaining the short-channel effects, it is pointed out that one should consider the lateral non-uniformity of the EVB tunneling current, which is related to the local variation of the threshold voltage V th .

This work presents a new method to extract the oxide charge densities at front ( Q ox1 ) and back ( Q ox2 ) interfaces of fully depleted SOI nMOSFETs. The proposed method is based on the influence of the front and back gate voltages on the back and front channel current regime, respectively. To extract Q ox2 , the drain current curve is measured as a function of the back gate voltage V GB with the front interface inverted. When the back interface condition changes due to the back gate voltage, kinks occur in the front drain current for specific V GB values which are used by the method. Similarly, the back drain current as a function of the front gate voltage V GB with the back interface inverted shows some kinks for specific V GF values which are used by the method to extract Q ox1 . MEDICI simulations were used to support the analysis and the method was applied experimentally.

This work presents a new method to extract the silicon film and front oxide thickness on fully depleted silicon-on-insulator nMOSFETs. The proposed method exploits the influence of the front/back gate voltages on the back/front channel current regime. To extract the silicon film thickness, the drain current curve is measured as a function of the back gate voltage V GB with the front interface inverted. When the back interface condition changes due to the back gate voltage, kinks occur in the front drain current for specific V GB biases and these are used by the method. Similarly, the back drain current as a function of the front gate voltage V GF with the back interface inverted shows some kinks at specific V GF , which are used by the method to extract the front oxide thickness. MEDICI simulations were used to support the analysis and the method was validated experimentally.

This paper describes the low-frequency noise behaviour of n-channel MOSFETs fabricated in a 0.1 μm technology. It is shown that the spectra are predominantly of the 1/f-type for some part of the frequency range investigated. For some devices, two 1/f-type parts occur, one at low and another at “high” frequencies, separated by a plateau. A careful analysis of the drain current or gate bias dependence of the noise spectral density reveals that the low-frequency 1/f-type noise is governed by the fluctuations in the series resistance region of the devices. The corresponding Hooge parameter αH is of the order of 10−4. For the 1/f-like noise occurring at “high” frequencies, it is observed that it can be ascribed to fluctuations in the channel, giving rise to a high value of αH of ∼10−3 (from 2.5×10−3–8×10−3).

We present a simple method to extract the eAective doping concentration related to the LDD (Lightly Doped Drain) regions in fully depleted SOI MOSFETs. The series resistance of an LDD structure MOSFET is composed of diAerent components, the LDD series resistance, being the dominant one. The proposed method uses the back gate voltage influence on the back interface below the LDD region. MEDICI simulations were used to support the analysis. Experimental results obtained from I‐V data were compared to the simulated results demonstrating a good agreement. 7 2000 Elsevier Science Ltd. All rights reserved.