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Abstract: This paper discusses the performance and reliability of aggressively scaled HfAlO x -based interpoly dielectric stacks in combination with high-workfunction metal gates for sub-45nm non-volatile memory technologies. It is shown that a less than 5nm EOT IPD stack can provide a large program/erase (P/E) window, while operating at moderate voltages and has very good retention, with an extrapolated 10-year retention window of about 3V at 150°C. The impact of the process sequence and metal gate material is discussed. The viability of the material is considered in view of the demands of various Flash memory technologies and direction for further improvements are discussed. [Copyright &y& Elsevier]

Abstract: In this study, the reliability (fatigue, imprint, and retention) of Pt/SBT/Pt capacitors was investigated. For non-integrated test capacitors, using a different process for top and bottom electrode formation, fatigue degradation is larger than for integrated capacitors using symmetric top and bottom electrode deposition process. Also, for the non-integrated capacitors, imprint behavior and retention loss were observed to depend on the voltage polarity. From hysteresis as well as leakage characteristics, these effects were attributed to the presence of a built-in field favoring the polarization of SBT from the bottom to the top electrode in non-integrated capacitors. The built-in field was attributed to defect generation during the top electrode sputtering at room temperature. For the integrated capacitors, whereby the top electrode is deposited using the same high temperature process (>150°C) as the bottom electrode, neither imprint degradation nor retention loss was observed under the applied conditions, showing excellent reliability of integrated SBT capacitors. [Copyright &y& Elsevier]