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• LVT and (U)HVT pMOS and nMOS device flavors with p- and n-WFM's are compared in terms of performance and reliability. • LVT flavors (pMOS w/ p -WFM and nMOS w/ n- WFM) show best performance (mobility and drive current) and best BTI reliability. • TiAl induces oxygen-scavenging, yielding a ∼1Å thinner EOT, a larger density of O-vacancies, and positive interface charge. • The fixed positive interface charge induced by TiAl is identified as the cause of enhanced NBTI in (U)HVT pMOS. • The PBTI of (U)HVT nMOS w/ p -WFM is found to be enhanced due to the additional contribution of deep HfO 2 defects. • These deep HfO 2 traps are instead kept in equilibrium by the gate Fermi level in the presence of a n -WFM (nMOS LVT). • An unified Comphy model is proposed to reproduce the PBTI and NBTI trends in nMOS and pMOS with different gate WFM. • Guidelines for correct multi- V th gate stack BTI benchmarking based on accelerated RVS test are provided. Multi- V th CMOS device technologies have become standard for System-on-Chip designs. In Replacement Gate technologies, distinct device V th 's are achieved by deploying different work function metal stacks, and thus concerns exist about the possible chemical interaction of different gate metals with the underlying dielectrics potentially affecting the device performance and reliability. We present a comprehensive study, comprising both electrical measurements and simulations, carried out on a planar transistor platform with state-of-the-art gate stacks. Two different metal stacks are deployed to fabricate low- V th and ultra-high V th pMOS and nMOS device flavors. The study provides fundamental insights on the impact of TiAl-based gate metal on EOT, gate leakage, interface quality, carrier mobility, short channel performance, PBTI and NBTI reliability. [ABSTRACT FROM AUTHOR]